Intrinsic decoupling capacitor

Details Intrinsic decoupling capacitor Intrinsic decoupling capacitor

2008-01-08

2008-01-08

Prenty, Mark V. (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

Passive components in ics

C257S371000, C257S204000

Reexamination Certificate

active

07317238

ABSTRACT:
A plurality of N-doped strip portions are formed alternating with a plurality of P-doped regions. When a voltage is applied to the N-doped strip portions, a capacitance is created between the N-doped strip portions and the P-doped strip portions. A capacitance is also created between the N-doped strip portions and the underlying epitaxial silicon layer. A larger interface area between N-doped and P-doped regions generally increases the capacitance. By providing the N-doped strip portions, as opposed to a continuous N-doped region, the combined interface area between the N-doped strip portions and the underlying epitaxial silicon layer is reduced. However, more interface area is provided between the N-doped strip portions and the P-doped strip portions. A circuit simulation indicates that junction capacitance per unit peripheral length is 0.41 fF/μm, while the junction capacitance per unit area is 0.19 fF/μm^2. Junction capacitance per unit peripheral length thus scales faster than junction capacitance per unit area.

REFERENCES:
patent: 3544862 (1970-12-01), Gallagher et al.
patent: 4017885 (1977-04-01), Kendall et al.

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