Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
1996-08-23
2001-04-24
Mengistu, Amare (Department: 2778)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
Reexamination Certificate
active
06222512
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a display device using the method of intraframe time-division multiplexing which reduces the gray-scale disturbance occurring when, for example, such a display devices as one using a gas discharge panel is used to display pictures, and to a method therefor.
2. Description of the Related Art
In recent years, as display devices have become larger, there has arisen a demand for thin display devices and a variety of thin display devices has been proposed.
Of these, there are display panels which have two stable operating states and, in order to perform multiple-level gray-scale display with such display panels, the method of intraframe time-division multiplexing is used.
However, when this method is used to display a picture, disturbance of the gray-scales causes a drop in picture quality, and this problem must be solved to achieve an improvement in picture quality.
In the past, intraframe time-division multiplexing was a method used for performing gray-scale display in display panels that had only two stable operating states, on and off.
In the past such devices as gas discharge display panels, liquid-crystal display panels, and fluorescent discharge display panels were used as display devices employing the method of intraframe time-division multiplexing, and an actual example of such a gas discharge display panel would be, for example, a plasma display device.
These intraframe time-division multiplexing type display devices have become small in depth and now have large areas, which has led to a sudden broadening of their applications and growth in production levels.
An actual example of a gas discharge panel which uses the intraframe time-division multiplexing method is described in the form of a plasma display device for the purpose of explaining the prior art in methods of performing gray-scale display.
Such flat plasma display devices generally use the electrical charge accumulated between electrodes to cause the emission of light, and this general display principle and the related construction and operation are described briefly below.
Well-known plasma display devices in the past (AC type PDP) include a two-electrode type in which selection discharge (address discharge) and sustained discharge are performed by two electrodes, and a three-electrode type in which a third electrode is used to perform address discharge.
Specifically,
FIG. 5
shows a simplified top plan view an example of the configuration of a three-electrode type plasma display device of the prior art, and
FIG. 6
shows a simplified cross-sectional view of one of the discharge cells
10
formed in the plasma display device of FIG.
5
.
This plasma display device, as can be seen in FIG.
5
and
FIG. 6
, is formed from two glass substrates
12
and
13
. The 1st glass substrate
13
is provided with 1st electrodes (X electrodes)
14
and 2nd electrodes (Y electrodes)
15
which act as sustaineding electrodes, which are disposed so as to be mutually parallel, these electrodes being covered by an electrolytic layer
18
.
In addition, a protective film of MgO (magnesium oxide) is formed, as covering film
21
, on the discharge surface represented by the electrolytic layer
18
.
On the surface of the 2nd glass substrate
12
, which is opposite the above-noted 1st glass substrate
13
, is formed a 3rd electrode
16
, which acts as an address electrode, and which disposed so as to be perpendicularly to the above-noted sustaineding electrodes
14
and
15
.
On top of the address electrodes
16
a phosphor
19
having a color emitting character of red, green, or blue is formed, this being located in the discharge space which is established by the wall
17
which is formed in the same plane in which is located the address electrodes of the above-noted 2nd glass substrate
12
.
That is, each of the discharge cells
10
of this plasma display device is separated by a wall (barrier).
In the actual example of a plasma display device noted above, the 1st electrodes (X electrodes)
14
and 2nd electrodes (Y electrode)
15
are disposed so as to be mutually parallel, each forming a pair, with the 2nd electrodes (Y electrodes)
15
being each separately driven by separate Y electrode drive circuits
4
-
1
to
4
-
n
which are connected to a common Y electrode drive circuit
3
, and with the 1st electrodes (X electrodes)
14
forming a common electrode and being driven by a single drive circuit
5
.
Perpendicularly crossing the X electrodes
14
and the Y electrodes
15
are the address electrodes
16
-
1
to
16
-
m
, these address electrodes
16
-
1
to
16
-
m
being connected to an appropriate address drive circuit
6
.
In this flat display device, each line of the address electrodes
16
is connected to the address driver
6
, the address driver
6
applying the address pulses to each of the address electrodes.
The Y electrodes
15
are each connected separately to the Y scan drivers
4
-
1
to
4
-
n.
The address scan drivers
4
-
1
to
4
-
n
are further connected to the common Y electrode driver
3
, with address discharge pulses being generated by the scan drivers
4
-
1
to
4
-
n
, and with sustained discharge pulses, etc. being generated by the common Y driver
33
shown in
FIG. 7
, these passing through the Y scan drivers
4
-
1
to
4
-
n
and being applied to the Y electrodes
15
.
The X electrodes
14
are commonly connected and driven across the entire display line of the panel of this flat display device.
That is, the common X electrode driver
5
(
32
in
FIG. 7
) generates write pulses and sustained pulses, these being applied in parallel to each of the X electrodes
14
.
These drive circuits are controlled by a control circuit (not shown in the drawings), this control circuit being in turn controlled by synchronization signals and display data signals applied from outside the device.
As described above, in a display panel
1
of a prior art flat display device, the above-noted sustained electrodes
10
are located so as to form a matrix of m in the horizontal direction and n in the vertical direction, with the Y side scan driver circuit
4
-
1
driving the Y electrodes that are connected to sustained discharge cells
10
that are uppermost in the vertical direction and arranged in a row of m cells, and in the same manner each of the Y side scan drive circuits
4
-
2
to
4
-
n
separately drive the Y electrodes which are the scan display lines corresponding to each of them.
The X electrode drive circuit
5
drives the X electrodes, which run in parallel to the Y electrodes, but which form a common electrode and are thus driven in common by a single X electrode driver circuit
5
.
FIG. 7
is a simplified block diagram which shows the peripheral circuitry which drives the plasma display shown in FIG.
5
and
FIG. 6
, in which address electrodes
16
are each connected separately to address driver
31
, this address driver
31
applying address pulses to each of the address electrodes at the time of address discharge.
The Y electrodes
15
are connected separately to a Y scan driver
34
.
This Y scan driver
34
is further connected to a common Y driver
33
, with pulses generated by the scan driver
34
at the time of address discharge, and sustained discharge pulses, etc. generated by the common Y driver
33
, passing through the Y scan driver
34
to the Y electrodes
15
.
The X electrodes
14
are connected in common across the entire display line of the panel of this flat display device.
That is, the common X electrode driver
32
shown in
FIG. 7
(
5
in
FIG. 5
) generates such pulses as write pulses and sustained pulses, these pulses being applied in parallel and simultaneously to each of the Y electrodes
15
.
The driver circuits are controlled by a control circuit, this control circuit being controlled by synchronization signals and data signals input from outside the device.
Specifically, as can be seen from
FIG. 7
, the address driver
31
is connected to the display data control section
36
provided i
Ishida Katsuhiro
Kariya Kyoji
Kuriyama Hirohito
Matsui Naoki
Tajima Masaya
Fujitsu Limited
Mengistu Amare
Staas & Halsey , LLP
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