Intra-unit column address increment system for memory

Details Intra-unit column address increment system for memory Intra-unit column address increment system for memory

1998-02-02

2001-06-12

Zarabian, A. (Department: 2824)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S230040, C365S236000

Reexamination Certificate

active

06246630

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to the design of a random access memory (RAM) and more specifically to circuitry which accesses and transfers data with a set of address inputs to and from a storage array within a RAM.
BACKGROUND OF THE INVENTION
Maximization of storage capacity and minimization of power usage and access time are goals in the design of integrated circuits (ICs, “chips”), especially as to ICs containing memory and logic arrays for use in data processing systems.
I. Row Decoder Design
To increase the storage capacity of a random access memory (RAM), it is important to find ways to reduce the amount of area occupied by circuitry other than the storage cell arrays of the RAM. One way in which this can be accomplished is by utilizing a shared row decoder design which permits wordlines in both left and right units of a bank division of the RAM to be accessed through the same set of row decoders, thus decreasing by half the number of row decoders required to perform that function. However, this goal is not well served if the reduction in decoder circuitry is made at the expense of increased access time or higher power consumption for the RAM, especially in cases where the design for a RAM chip requires a plurality of banks.
FIG. 1
shows an example of a 32 Mb double unit
10
which includes left and right units
12
,
20
, left and right wordline (WL) driver units
14
,
18
, and a shared row decoder unit
16
which receives inputs including row predecoded addresses XP
1
. . . XPn, and block select inputs BLKSELs. This 32 Mb double unit organization has been incorporated into an existing design for a 256 Mb DRAM, the details of which are described in the Article by Y. Watanabe et al. entitled “A 286 mm2 256 Mb DRAM with x32 Both-Ends DQ,”
IEEE Journal of Solid-State Circuits
, Vol. 31, No. 4, April, 1996 (“the Watanabe Article”). Within the shared row decoder unit
16
there are provided a plurality of row decoders
30
, the structure of which is shown in FIG.
2
.
As shown in
FIG. 2
, each row decoder
30
of shared row decoder unit
16
(
FIG. 1
) receives as inputs a plurality of row predecoded addresses, for example three predecoded addresses (XP
1
, XP
2
, XP
3
), and a block select signal BLKSEL. Upon receiving the correct combination of row predecoded addresses XPs to enable the row decoder
30
at a time when the BLKSEL signal is active, the row decoder
30
activates a row decoder output signal RDOUT which is provided to both a left WL driver
14
and a right WL driver
18
of the double unit
10
. In this way, only one row decoder
30
is needed to enable the selection of blocks from both left and right units,
12
,
20
.
In operation, the BLKSEL signal is held active during a time in which both units
12
,
20
are in an active state. During a reset phase, when the BLKSEL signal enters an inactive state again, RDOUT signals of row decoders
30
are precharged to HIGH, at which time units
12
,
20
are simultaneously deactivated.
It will be understood that the row predecoded addresses XPs must hold the information constant for the duration in which BLKSEL is active. Otherwise, RDOUT might be falsely enabled by the XPs transition between states because the XPs provide the enabling and trigger conditions for RDOUT.
Because the row decoder
30
requires the XPs to hold the information constant during BLKSEL active cycles, it is not possible to use row decoder unit
30
in a double unit
10
in which it is desired to utilize each unit
12
,
20
as a separate bank under separate row addressing control. That is, row decoder
30
cannot be used in a double unit
10
which is configured to operate as two or more banks.
FIG. 3
shows a schematic for the design of another existing row decoder unit
40
which permits a pair of left and right units
12
,
20
to be configured as a pair of banks, rather than just a single bank, as is the conventional configuration. Row decoder unit
40
includes sets of row decoder circuits
42
for each of the left unit
12
and the right unit
20
which are completely independent from each other, i.e. the decoder circuits
42
in each set include independent devices which receive and act upon the row predecoded addresses and block select signals to activate wordlines within the respective left and right units,
12
,
20
. Consequently, left and right units
12
,
20
can each be independently controlled, to access storage locations at different row addresses at the same time.
However, row decoder unit
40
, which duplicates the input and output circuits for all predecoded address and block select inputs, requires twice the number of row predecoded address signal lines and row decoder circuits
42
as row decoder unit
16
. In consequence, the area occupied by row decoder unit
40
on an IC is substantially greater than the area occupied by row decoder unit
16
. It would be advantageous to provide a row decoder unit which permits a double unit to be configured with multiple banks, without requiring row decoder circuits therein to be duplicated.
Accordingly, it is an object of the invention to provide a row decoder circuit of a row decoder unit which permits a plurality of banks to be configured within a pair of memory units, i.e. a pair of physically contiguous memory arrays served by the row decoder unit, while reducing the amount of area occupied by the row decoder unit.
It is another object of the invention to provide a row decoder unit which reduces the consumption of current while permitting a double unit to be configured as multiple banks.
II. Block Address Assignment Within Banks
In an existing RAM (as shown, for example, in FIG.
1
), blocks are arranged in the same way within left and right units
12
,
20
, namely, numbered in sequential order from bottom to top (or from top to bottom). As such, blocks which are accessed by the same address inputs are located across from each other at the same distance away from the ends
22
of the units
12
,
20
. That is, block
0
in the left unit
12
is located across from block
0
in the right unit
20
and lies at the end
22
of the left unit
12
, as does block
0
in the right unit
20
. In the same way, block
1
in the left unit is located across from block
1
in the right unit
20
and lies one block away from the end
22
of the left unit
12
, as does block
1
in the right unit
20
.
However, the inventors have found that addressing blocks within the left and right units
12
,
20
in such symmetrical fashion is undesirable. Within a unit
12
, one or more wordlines in a block are activated at a time by signals supplied to the row decoder from one end
22
of the unit
12
. As described above with reference to
FIG. 3
, units
12
,
20
can be accessed independently in an ACTIVE mode when double unit
10
is configured as multiple banks, each bank having independent row decoder circuits
42
. However, when double unit
10
is configured as a single bank, units
12
,
20
are not independently controlled, such that the row decoder unit
16
accesses the same physical block numbers across both units
12
,
20
. Even when the double unit
10
is configured as multiple banks, when the double unit
10
is operated in known Column-Address-Strobe (CAS) Before Row-Address-Strobe (RAS) Refresh mode (CBR mode), locations will be accessed within each unit
12
,
20
with signals selecting the same block numbers in both units
12
,
20
. Thus, in CBR mode, whether in a single bank unit or in a double unit having a multiple bank configuration, wordlines in the same numbered blocks in both left and right units
12
,
20
are alternately or simultaneously accessed, first from one unit, for example, the left unit
12
, then from the other unit, i.e. the right unit
20
in this example.
When high numbered blocks are accessed, e.g block
15
in the left and right units
12
,
20
, the greater length of signal travel (and consequent voltage drop) from the end
22
of the units
12
,
20
to such blocks requires more current to be supplied than that required to access low-

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