Boots – shoes – and leggings
Patent
1976-09-14
1978-07-04
Zache, Raulfe B.
Boots, shoes, and leggings
G06F 104
Patent
active
040992322
ABSTRACT:
An interval timer in a MOS IC microprocessor system uses a countdown register of as many stages as the data bus lines (8) but effectively doubles the capacity of that register, without increasing the number of data bus lines or repetitive loading, by interposing a prescale divide-down register between the system clock and the countdown register. The prescale register divides the system clock by one of several selectable factors equal to non-contiguous powers of two (e.g., by 1, 8, 64 or 1,024) to establish respective prescale time periods (of 1, 8, 64 or 1024 system clocK pulses). One of the several possible prescaling factors is selected by a pair of lines from the system address bus. As a result, the interval timer can be configured with one load operation for an interval within a range which was possible in the prior art only with double the number of data lines and double the length of the countdown register. Chip layout is thus optimized, and the number of control lines needed to access timer functions is reduced, with acceptable loss of flexibility.
REFERENCES:
patent: 3812472 (1974-05-01), Mahood
patent: 3867614 (1975-02-01), White
patent: 3878370 (1975-04-01), Santomango et al.
MOS Technology, Inc.
Zache Raulfe B.
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