Intersystem fault detection and bus cycle completion logic syste

Details Intersystem fault detection and bus cycle completion logic syste Intersystem fault detection and bus cycle completion logic syste

1981-08-27

1985-06-04

Zache, Raulfe B.

Boots, shoes, and leggings

G06F 304, G06F 946

Patent

active

045218480

ABSTRACT:
An error detection system is disclosed for not only indicating but eliminating certain errors which may occur during the transfer of information between communication busses in a data processing system wherein plural communication busses each provide a common information path to plural data processing units including memory units, peripheral control units, central processing units and ISL units, and wherein each of the plural communication busses are in electrical communication with an ISL unit, and ISL units are electrically connected in pairs. The error detection system requires no special supporting software or firmware on the part of any data processing unit on any of the communication busses.

REFERENCES:
patent: 3566368 (1971-02-01), Blauw
patent: 3993981 (1976-11-01), Cassarino
patent: 4041472 (1977-08-01), Shah
patent: 4052702 (1977-10-01), Smith
patent: 4090239 (1978-05-01), Twibell

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