Boots – shoes – and leggings
Patent
1989-01-17
1991-01-22
Chan, Eddie P.
Boots, shoes, and leggings
3642383, 3642386, 364239, 3642397, 3642412, 3642421, 3642422, 3642632, G06F 700
Patent
active
049875353
ABSTRACT:
An interrupt control circuit is configured as a memory circuit to output interrupt vector information in response to multilevel interrupt requests for a CPU. The interrupt control circuit is provided with a plurality of interrupt vector generators configured as a memory matrix array. Each interrupt vector generator effects self-addressing based on the contents of a memory cell functioning as a latch circuit in which is stored an interrupt request and the contents of a memory cell functioning as a mask register in which interrupt control information is stored. The interrupt control circuit is further provided with a single output buffer commonly coupled to memory cells constituting each interrupt vector generator, thereby providing access to a self-addressed interrupt vector generator to concurrently output the interrupt vector information from the respective memory cells to a data bus via the single output buffer. A small-sized interrupt control circuit having a high signal transmission speed is thereby provided.
REFERENCES:
patent: 3999165 (1976-12-01), Kita et al.
patent: 4004283 (1977-01-01), Bennett et al.
patent: 4200912 (1980-04-01), Harrington et al.
patent: 4315314 (1982-02-01), Russo
patent: 4349872 (1982-09-01), Fukasawa et al.
Intel Data Component Catalog 1981, Intel Corporation, Santa Clara, CA, pp. 123-139.
Chan Eddie P.
NEC Corporation
Rudolph Rebecca L.
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