Interrupt transfer management process and system for a multi-pro

Details Interrupt transfer management process and system for a multi-pro Interrupt transfer management process and system for a multi-pro

1996-07-01

1998-11-24

An, Meng-Ai T.

Multiplex communications

Wide area network

Packet switching

395293, 395739, 395737, 395741, 370242, G06F 1324

Patent

active

058420266

ABSTRACT:
An interrupt mechanism handles an interrupt transaction between a source processor and a target processor on separate nodes in a multi-processor system. The nodes are connected to a network through node interface controls between the node and the network. The transaction begins by initiating the interrupt transaction at the source processor. The interrupt mechanism detects if the target processor is at a remote node on a system bus across the network, and if it is the mechanism sends an ignore signal to the source processor. Then the mechanism suspends the interrupt transaction at the source processor if it detects the target processor is at a remote node. The mechanism performs an ACK/NACK (acknowledge
on-acknowledge) operation at the target processor and returning an ACK signal or a NACK signal to the source processor across the network. This ACK/NACK signal wakes-up the source processor. The source processor sends interrupt data to the target processor if an ACK signal is received and aborts the interrupt transaction if a NACK signal is received.

REFERENCES:
patent: 5469542 (1995-11-01), Foster et al.
patent: 5560019 (1996-09-01), Narad
patent: 5630059 (1997-05-01), Brady et al.
patent: 5630077 (1997-05-01), Krein et al.
patent: 5633857 (1997-05-01), Kim et al.
patent: 5664200 (1997-09-01), Barlow et al.

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