Interrupt system using masking register in processor for selecti

Details Interrupt system using masking register in processor for selecti Interrupt system using masking register in processor for selecti

1985-06-28

1988-10-18

Zache, Raulfe B.

Boots, shoes, and leggings

G06F 1324

Patent

active

047791950

ABSTRACT:
Each processor in a system using the interrupt generation scheme has an external interrupt register (EIR) an input/output EIR (IO.sub.-- EIR) and an external interrupt mask register (EIM). When an I/O device wants to interrupt a first processor the I/O device writes a predetermined value to the first processor's IO.sub.-- EIR. When the predetermined value is written into the first processor's IO.sub.-- EIR, this causes a specified bit in the first processor's EIR to be set (or cleared depending upon system convention) and an interrupt to occur. The specified bit in the EIR indicates to the first processor either the I/O device which caused the interrupt, or a group of I/O devices which includes the I/O device which caused the interrupt. An I/O device can cause a bit in the EIR to be set, but only a processor can clear bits set in its EIR. The EIM is used by the processor to postpone taking action on an interrupt received from an I/O device. The processor takes action on an interrupt when an I/O device causes a bit to be set in the EIR, and a corresponding bit in the processor's EIM is set. If the corresponding bit in the EIM is not set, then the processor delays action on the interrupt until the corresponding bit in the EIM is set.

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