Interrupt status register for interface adaptor chip

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G06F 304, G06F 918

Patent

active

040695107

ABSTRACT:
A peripheral interface adaptor (PIA) circuit for data processing systems contains memory elements or control registers allowing modification under program control of the logical functions of the PIA.
A peripheral interface adaptor includes a plurality of data bus buffer circuits coupled to a bidirectional data bus and further includes peripheral interface buffer circuits coupled to a bidirectional peripheral data bus. A direction of data flow at the peripheral interface data bus is controlled by a data direction register. Data from the data bus buffer is entered into an input register, and is transferred from there to an input bus coupled to the control register, the data direction register and a data register. Data from the peripheral data bus the data direction register and the control register are transferred via the output bus to the data bus buffers. Control circuits include an interrupt/status logic circuit for transmitting control signals to and receiving interrupt signals from a peripheral unit coupled to the interface circuit.

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