Interrupt request controller for data processing system

Details Interrupt request controller for data processing system Interrupt request controller for data processing system

1977-02-17

1978-11-21

Nussbaum, Mark E.

Boots, shoes, and leggings

G06F 1308, G06F 919

Patent

active

041268938

ABSTRACT:
A memory control processor adapted to expand a random access or accelerator memory by logical overlays which performs these overlays into memory fields (pages) on the basis of page usage history. To provide a quick reference to page use a chronological sequence is established by links rather than by reordering a stack. This link sequence is tied by very limited leads to the rest of the memory control processor and can therefore be updated during each memory access. In addition the memory control processor includes a task priority logic integrating various competing memory access requests with the overlay operations. To achieve the various transfer modes in the quickest time the memory control processor is organized around a wide control memory storing the task servicing sequences. The width of the control memory and the associated task logic allow general purpose microprogrammable direct memory access which may further be utilized in multiplexed fashion to accommodate various concurrent tasks.

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