Interrupt pre-processor with dynamic allocation of priority leve

Details Interrupt pre-processor with dynamic allocation of priority leve Interrupt pre-processor with dynamic allocation of priority leve

1981-06-11

1984-03-20

Thomas, James D.

Boots, shoes, and leggings

365 49, G06F 900, G06F 946

Patent

active

044384890

ABSTRACT:
Interrupt requests of different priorities, presented by various interrupt sources (0 to 3), are transferred through control ST, in an associative storage and selection process, into preprocessing elements PE0 and PE1. These elements are variably assigned by controls ST to receive and preprocess requests of associated priority. The preprocessing generates a starting address of a program routine for servicing the respective request. This address is transferred to a common processor which executes the routine. The preprocessing elements can be structured to rapidly generate a succession of different starting addresses relative to several interrupt requests having the priority assigned to that element.

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patent: 4374413 (1983-02-01), Comfort et al.
J. D. Erwin et al., Interrupt Processing with Queued Content-Addressable Memories, Fall Joint Computer Conference, (Nov. 1970), pp. 621-627.

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