Interrupt driven, separately clocked, fault tolerant processor s

Details Interrupt driven, separately clocked, fault tolerant processor s Interrupt driven, separately clocked, fault tolerant processor s

1991-06-06

1993-08-03

Canney, Vincent P.

Excavating

395575, 371 683, G06F 1118

Patent

active

052336158

ABSTRACT:
A N-modular redundancy fault tolerant computing system comprises a plurality of microprocessors having their data outputs applied simultaneously to a voter. In accordance with this invention, the system can be event driven while still maintaining synchrony. This is accomplished by providing timing means for establishing a predetermined program execution interval comprised of a fixed number of clock cycles for the plurality of computer means of the N-modular fault tolerant system, the timing means assuring that all of said computer means achieve an identical machine state at the end of the predetermined program execution interval.

REFERENCES:
patent: 4497059 (1985-01-01), Smith
patent: 4733353 (1988-03-01), Jaswa
patent: 4937741 (1990-06-01), Harper et al.
patent: 5193175 (1993-03-01), Cutts, Jr. et al.
The Fifteenth Annual International Symposium on Fault-tolerant Computing, Jun. 19-21, 1985, pp. 246-251, IEEE, N.Y., U.S.; T. Yoneda et al, "Implementation of Interrupt Handler for Loosely-Synchronized TMR Systems" (see p. 246, right col., line 26-p. 248, right col., line 39, FIGS. 1-5).

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