Interrupt distribution scheme for a computer bus

Details Interrupt distribution scheme for a computer bus Interrupt distribution scheme for a computer bus

1993-01-28

1994-01-25

Fleming, Michael R.

Boots, shoes, and leggings

395325, 395725, 364229, 3642292, 364230, 3642302, 3642318, 3642327, 3642412, 3642426, 36424292, 364243, 3642434, 36424341, 364DIG1, G06F 946

Patent

active

052822729

ABSTRACT:
A method of handling processor to processor interrupt requests in a multiprocessing computer bus environment is described. This method allows a multiple-tiered, increasing priority, interrupt request scheme. This method also allows processor to processor directed interrupt requests, processor to one processor of a group of processors interrupt requests, and processor to all processors of a group of processors interrupt requests.

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