Interrupt controller with selectable interrupt nesting function

Details Interrupt controller with selectable interrupt nesting function Interrupt controller with selectable interrupt nesting function

1993-01-25

1995-04-25

Lee, Thomas C.

Boots, shoes, and leggings

364DIG1, 3642422, 3642412, 3642416, G06F 1326

Patent

active

054107156

ABSTRACT:
An interrupt controller comprises a circuit for holding information obtained by designating one priority selected from a plurality of priorities for each of a plurality of interrupt requests, and a flag for indicating whether or not a nesting is allowed for an interrupt request having at least one predetermined priority of the plurality of priorities. On the basis of the priority information held in the circuit and information held in the flag, a controller operates so that when an interrupt request is generated in the course of execution of an interrupt processing having the predetermined priority, if the flag is in a first condition, the controller acknowledges the generated interrupt request only when the priority of the generated interrupt request is higher than the predetermined priority, and if the flag is in a second condition, the controller acknowledges the generated interrupt request not only when the priority of the generated interrupt request is higher than the predetermined priority, but also when the priority of the generated interrupt request is the same as the predetermined priority.

REFERENCES:
patent: 4398244 (1983-08-01), Chu et al.
patent: 4488227 (1984-12-01), Miu et al.
patent: 4918599 (1990-04-01), Hashimoto et al.
patent: 5050067 (1991-09-01), McLagan et al.
Mano, Computer System Architecture, 1982, pp. 434-435.

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