Interrupt-controlled thread processing

Details Interrupt-controlled thread processing Interrupt-controlled thread processing

1998-12-22

2001-08-14

Cuchlinski, Jr., William A. (Department: 3661)

Data processing: generic control systems or specific application

Specific application, apparatus or process

Electrical power generation or distribution system

C712S207000, C712S210000, C712S212000, C712S222000, C712S228000, C709S241000, C709S241000, C709S241000, C709S241000, C710S260000

Reexamination Certificate

active

06275749

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to thread-oriented processing and, in particular, to multiple-thread processing by the use of contexts.
2. Description of Related Art
In multiple-thread processing, a processor is capable of successively performing a plurality of different processes (commonly referred to as “threads”). Upon the occurrence of a particular event, such as after the elapse of a predetermined time period or upon the receipt of a specific command, the processor suspends performance of one thread, stores a context describing the status of the thread being suspended, and begins performing another thread, which is also described by a respective context. Each “context” describes information needed for the processor either to initiate operation on a new thread or to continue operation on a suspended thread. Typically this information identifies memory addresses containing the initial or next operation of a respective thread to be performed and any data to be operated on.
In order to provide direct and rapid access to stored thread contexts, some processors include multiple banks of local context registers. This, however, is an inflexible arrangement which limits to a fixed quantity the number of threads that can be performed. It is also inefficient whenever the number of threads is smaller than the number of register banks provided.
Alternatively, the multiple contexts can be stored in a separate memory. Various examples of such an approach are described in U.S. Pat. No. 5,349,680. In one of these examples, described in the patent as a conventional information processing apparatus, a main processor includes both an application supporting unit for successively performing operations from different application processes and a system supporting unit for controlling the operation in the information processing apparatus. The efficiency of this arrangement is described as inferior, because the application supporting unit and the system supporting unit are never operated at the same time. U.S. Pat. No. 5,349,680 proposes alternative arrangements utilizing multiple stored contexts, but each of these arrangements requires the use of two separate processors. This is an expensive way to improve efficiency.
SUMMARY OF THE INVENTION
It is an object of the invention to enable rapid and efficient multiple-thread processing by a single processor that does not suffer from the inflexibility of utilizing a fixed number of local context registers.
This and other objects are achieved by utilizing interrupt-controlled swapping of contexts between a processor and a memory. This enables rapid multiple-thread processing with a minimum of hardware and also has the advantage of conserving electrical power requirements. In accordance with the invention, a method is employed which includes:
associating each of the interrupts with a predetermined remote memory location;
storing in the predetermined locations a plurality of thread context pointers, each of said pointers identifying a remote memory location for containing a thread context associated with one of said threads;
producing, in response to the occurrence of any of the interrupts, an address identifying the associated memory location;
reading the thread context pointer from the memory location identified by the address;
reading the thread context from the memory location identified by the thread context pointer read; and
performing the thread associated with the thread context read.
Note that the word “memory”, as used herein, is intended to be interpreted as generally as is consistent with the manner in which it is used and includes, without limitation, volatile and non-volatile devices of various types, such as registers, RAMs, DRAMs, ROMs etc. Further, “local memory” means a memory included in the processor and “remote memory” means a memory not included in the processor. Additionally, “copying” means reading information from one memory and writing it into another.


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