Patent
1996-06-25
1998-05-12
Harvey, Jack B.
395734, G06F 1332
Patent
active
057520437
ABSTRACT:
An interrupt control system is provided in a computer having a processor, a PCI bus, an ISA bus, and a serial transfer line. Serial interrupt request signals sent via the serial transfer line are converted into ISA interrupt request signals. Ones of ISA interrupt request signals sent via the ISA bus and the ISA interrupt request signals subjected to serial/parallel conversion are selected for each of same priority levels therebetween. Priority levels are allocated to PCI interrupt request signals sent via the PCI bus. Ones of the PCI interrupt request signals allocated priority levels and the ISA interrupt request signals selected by the first selecting circuit are selected for each of same priority levels therebetween. Polarity of ones of the PCI interrupt request signals and the ISA interrupt request signals selected by the first selecting circuit is reversed, so that the polarity of signals is unified. In response to the interrupt request signals whose polarity has been unified, an interrupt controller outputs interrupt requests to the processor according to the priority levels of the received signals. The interrupt controller fixes sensing type in receiving the signals to one of a edge sensing type and a level sensing type.
REFERENCES:
patent: 5506997 (1996-04-01), Maguire et al.
patent: 5619703 (1997-04-01), Omid et al.
patent: 5673400 (1997-09-01), Kenny
Chung-Trans Xuong
Harvey Jack B.
Kabushiki Kaisha Toshiba
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