Interrupt control for multiprocessor system with storage data co

Details Interrupt control for multiprocessor system with storage data co Interrupt control for multiprocessor system with storage data co

1982-06-25

1985-01-22

Zache, Raulfe B.

Boots, shoes, and leggings

G06F 1516

Patent

active

044955693

ABSTRACT:
A multiprocessor system includes a random access memory (85) for storing a processor number data specifying that an interrupt from any of a plurality of devices (6l to 6m) to any one of a plurality of processors (1l to 1n) is permitted. If and when an interrupt request signal is applied from the device (61) to an interrupt controller (8), a processor number data indicating a processor which the device (61) can interrupt is read out from the random access memory (85). The interrupt controller (8) applies an interrupt signal to a processor (11), for example, according to the processor number data. Correspondingly, the processor (11) applies a bus request signal to a bus controller (7). According to the bus request signal, the bus controller (7) controls a bus selecting circuit (3) to connect a local bus (21) of the processor (11) to a common bus (5).

REFERENCES:
patent: 4396978 (1983-08-01), Hammer et al.

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