Interrupt control for multiprocessor computer system

Details Interrupt control for multiprocessor computer system Interrupt control for multiprocessor computer system

1990-08-14

1992-06-23

Fleming, Michael R.

Boots, shoes, and leggings

3642302, 364941, 364DIG1, 364DIG2, G06F 1324

Patent

active

051250934

ABSTRACT:
A technique that efficiently allocates the servicing of interrupts among a plurality of CPUs in a multiprocessor computer system requires no change in software that was written for a system with one CPU and one PIC. Symmetric and asymmetric configurations contemplate a primary CPU (15a) and one or more secondary CPU's (15b-d) responding to and servicing multiple sets of interrupts. Both configurations include interrupt supervisory logic to support such operation. The symmetric configuration provides a PIC (20a-d) for each CPU in the system. All the PICs are located at the same I/O address, and separate provision is made to specify which PIC is to respond to an interrupt acknowledge cycle initiated by a particular CPU. The asymmetric configuration of the present invention provides PIC (20a) for the primary CPU (15a) only. That PIC's interrupt line is communicated only to the primary CPU. Another mechanism, such as an ATTN facility (95), is provided to drive the secondary CPU's interrupt inputs. Since the secondary CPUs lack PICs there is provided logic (48) that responds to an interrupt acknowledge operation from any of the secondary CPUs by driving a fixed, interrupt vector onto the data bus.

REFERENCES:
patent: 4149243 (1979-04-01), Wallis
patent: 4495569 (1985-01-01), Kagawa
patent: 4598356 (1986-07-01), Dean et al.
patent: 4604500 (1986-08-01), Brown et al.
patent: 4722048 (1988-01-01), Hirsch et al.
patent: 4935866 (1990-06-01), Sauvajol et al.

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