Interrupt control circuit for multi-master bus

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Details

364DIG1, 3642217, 3642302, G06F 1314

Patent

active

051095130

DESCRIPTION:

BRIEF SUMMARY
DESCRIPTION

1. Technical Field
This invention relates to an interrupt control circuit for a multi-master bus, more particularly, an interrupt control circuit adapted to a multi-master bus suitable for a multi-processor system for the realization of FA (factory automation).
In the field of FA using NC machine tools, recently, a complicated and advanced controls such as visual monitoring of controlled objects, for example, tools and robots, with a television camera, analyzing the monitored image using an image analyzing apparatus, and feeding back information to the controller, has been realized. As a method for rapidly carrying out this complicated and advanced control, a technique of connecting a plurality of processors to each other by a multi-master bus has been employed in order to distribute the overall process among the processors to reduce the load on each processor, and to have rapid communication between the processors. The interrupt control circuit of the present invention is provided for a multi master bus suitable for a system realizing complicated and advanced FA by connecting a plurality of processors to each other by a multi-master bus.
2. Background Art
In a system where a plurality of processors or modules is connected to each other by a multi-master bus, transmission or exchange of an interrupt signal from one processor or module to another is performed through a multi-master bus. In this case, an interrupt control circuit for each module comprises a bus interface and a vector number generating circuit. The bus interface includes an interrupt status register provided at least on a one-to-one basis in each module for exchanging interrupt signals and for delivering the interrupt signals to each other. Namely, a bus interface belonging to a module trying to effect an interrupt responds to a command from a CPU belonging to the module and outputs a control signal to be written in a predetermined bit in an interrupt status register of a bus interface belonging to a module being addressed. This signal is output during a bus not busy state in the multi-master bus and reaches the bus interface of the addressed module through the multi-master bus. If any bit of the interrupt status register of the bus interface becomes 1 (true), the OR of all the bits becomes 1, which is then input into the vector number generating circuit. In addition to the signal from the bus interface, interrupt signals from input/output circuits, etc., which the CPU directly drives, are input into the vector number generating circuit. The vector number generating circuit outputs an interrupt signal to the CPU when one of its input terminals becomes 1.
In the case of an interrupt from other modules in the interrupt control circuit having this construction, software processes for reading out the content of the interrupt status register and branching in response to the content are necessary, and therefore, considerable time is necessary for the software processes.
Generally software is divided into several tasks according to the gist of the processes, and event-driven type real-time processing is executed under management of a real-time monitor which manages the tasks. In this case, an increase in the processing time of the interrupt processing software leads to an increase in overhead time, and the ability of the overall system is decreased remarkably.


DISCLOSURE OF THE INVENTION

It is an object of the present invention to improve on the aforementioned drawbacks in the conventional interrupt control circuit used in an FA system wherein a multi-master bus connects plurality of processors to each other so as to increase performance of the overall system.
This object is carried out by an interrupt control circuit for a multi-master bus accepting various kind of interrupt requests including external interrupt requests from other modules, through a multi-master bus connecting numerous modules, including a plurality of bus masters, to each other and generating interrupt vector numbers corresponding to the kind of interrupt requests

REFERENCES:
patent: 4420806 (1983-12-01), Johnson, Jr. et al.
patent: 4796176 (1989-01-01), D'Amico et al.
patent: 4803613 (1989-02-01), Kametani et al.

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