Interrupt control circuit

Details Interrupt control circuit Interrupt control circuit

1977-03-18

1978-07-25

Thomas, James D.

Boots, shoes, and leggings

G06F 918

Patent

active

041033272

ABSTRACT:
Processor circuitry is disclosed for setting a memory address register to a predetermined address upon the receipt of an interrupt request. The receipt of the request extends a steady state signal through an AND gate to the input of the counter to hardwire jam it to a predetermined address which defines the memory location of the first word of a subroutine associated with the request. The jam signal remains on the register input until the addressed memory location is read out. A readout of this location disables the AND gate and removes the jam signal from the counter. The AND gate is restored to normal when the last word of the subroutine is read out to permit new interrupt requests to be honored. The continuous application of the jam signal to the register until the addressed location is read out increases the probability of the register being successfully set to the correct address.

REFERENCES:
patent: 3309672 (1967-03-01), Brun

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