Patent
1996-08-15
1998-10-06
Pan, Daniel H.
395876, 395889, G06F 1340, G06F 13376
Patent
active
058191143
ABSTRACT:
A computer system employs systems and methods that are transparent to the operating system and application programs, for interruption recovery and resynchronization of events including a playback FIFO buffer having an underrun counter that counts the number of audio samples that could not be read from the playback FIFO buffer because the playback FIFO buffer was empty. When the playback FIFO buffer goes empty, an interrupt is asserted to signal the processor to read the underrun counter to determine how many samples it missed and to advance its pointers forward to "re-sync" the data stream. The computer system further preferably includes a capture FIFO buffer to capture samples from an ADC and having an overrun counter that counts the number of audio samples that could not be written to the capture FIFO buffer because the capture FIFO buffer was full. The capture FIFO buffer generates an interrupt to signal the processor to read the overrun counter to determine how many samples it missed and to fill a record buffer with a number of samples equal to the overrun count, wherein each sample has a predetermined value preferably equal to the value of the last input before overrun.
REFERENCES:
patent: 5388261 (1995-02-01), Anderson et al.
patent: 5392396 (1995-02-01), MacInnis
patent: 5517521 (1996-05-01), Strawn
Maxin John L.
National Semiconductor Corporation
Pan Daniel H.
LandOfFree
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