Interprocessor switching network

Details Interprocessor switching network Interprocessor switching network

1987-11-13

1989-12-05

Olms, Douglas W.

Multiplex communications

Wide area network

Packet switching

3408255, H04Q 1104

Patent

active

048857394

ABSTRACT:
A message transport network (10) is provided for high speed switching between processing elements (72, 80). Clusters of low speed processing elements (72) may be connected to the message transport network (10) through a transport node controller (78). The transport node controller (78) and the high speed processors (80) are connected to the gateways (82). A pair of gateways (82) may be connected through a transport interchange node (106) to allow communication between processors (72, 80) associated with the gateways (82). A transport interchange supervisor (98) maintains a record of the status of each gateway (82) and generates commands to form connection between gateways (82) in the transport interchange node (106). A maintenance controller (102) and system maintenance processor (76) oversee the validity of the data being passed through the system on paths independent of the data transfer paths. The message transport network (10) may be used in a variety of applications, such as a telphony switch (11), a signaling transfer point system (21) or a fault tolerant minicomputer (49).

REFERENCES:
patent: 3226687 (1965-12-01), Amdahl et al.
patent: 3226688 (1965-12-01), Amdahl et al.
patent: 3226689 (1965-12-01), Amdahl et al.
patent: 3226692 (1965-12-01), Fuller et al.
patent: 3274561 (1966-09-01), Hallman et al.
patent: 3411139 (1968-11-01), Lynch et al.
patent: 3419849 (1968-12-01), Anderson et al.
patent: 3651473 (1972-03-01), Faber
patent: 3749845 (1973-07-01), Fraser
patent: 3753234 (1973-08-01), Gilbert et al.
patent: 3768074 (1973-10-01), Sharp et al.
patent: 3787816 (1974-01-01), Hauck et al.
patent: 3876987 (1975-04-01), Dalton et al.
patent: 3905023 (1975-09-01), Perpiglia
patent: 3916380 (1975-10-01), Fletcher et al.
patent: 3984819 (1976-10-01), Anderson
patent: 4044333 (1977-08-01), Auspurg et al.
patent: 4075693 (1978-02-01), Fox et al.
patent: 4099233 (1978-07-01), Barbagelata et al.
patent: 4130865 (1978-12-01), Heart et al.
patent: 4155117 (1979-05-01), Mitchell, Jr. et al.
patent: 4166929 (1979-09-01), Sheinbein
patent: 4191941 (1980-03-01), Springer et al.
patent: 4195344 (1980-03-01), Yamazaki
patent: 4204251 (1980-05-01), Brudevold
patent: 4387441 (1983-06-01), Kocol et al.
patent: 4433376 (1984-02-01), Lombardo, Jr. et al.
patent: 4438494 (1984-03-01), Budde et al.
patent: 4482996 (1984-11-01), Wilson et al.
patent: 4516238 (1985-05-01), Huang et al.
patent: 4550402 (1985-10-01), Gable et al.
patent: 4598400 (1986-07-01), Hillis
patent: 4611322 (1986-09-01), Larson et al.
patent: 4630258 (1986-12-01), McMillen et al.
patent: 4698841 (1987-10-01), Haselton et al.
"Butterfly Parallel Processing Computer", Bolt Beranek and Newman, Inc., brochure, undated.

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