Interprocessor communications includes second CPU designating me

Details Interprocessor communications includes second CPU designating me Interprocessor communications includes second CPU designating me

1990-01-26

1992-06-16

Lee, Thomas C.

Boots, shoes, and leggings

364DIG1, 3642281, 3642283, 3642412, 364247, 364243, 364246, G06F 946

Patent

active

051230941

ABSTRACT:
A method for performing inter-processor communications in a multiprocessor system combines the sending of a message with the sending of a message interrupt. Messages are exchanged through a shared memory organized into pages, each of which may be "owned" by a processor. When a sending processor executes a store instruction that stores its operand to a memory area owned by a destination processor, a message interrupt is presented to the destination processor. If the destination processor is interrupt enabled, the operand of the store instruction is stored at the address specified by the store instruction and that address is stored in a register of the destination processor. Execution of the store instruction by the sending processor then completes.

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