Interprocessor communications data transfer and error detection

Details Interprocessor communications data transfer and error detection Interprocessor communications data transfer and error detection

1996-05-23

1998-11-24

Asta, Frank J.

Multiplex communications

Wide area network

Packet switching

39520062, 395290, 39520039, 395308, 395309, 370462, G06F 1314, G06F 1348, G06F 1342

Patent

active

058419888

ABSTRACT:
A multiprocessing system includes a plurality of data processing subsystems each coupled to an interprocessor communications bus through a corresponding interprocessor communications interface. The interprocessor communications interface corresponding to each data processing subsystem includes a receive FIFO buffer unit, a transmit FIFO buffer unit, and a control circuit. When a data processing subsystem desires to transfer data to another processing subsystem, the data processing subsystem packetizes the data in a variable word-length transfer packet which includes a header having a size field and a target field. The data processing subsystem causes the transfer packet to be stored within the transmit FIFO buffer unit. When a valid transmit packet is stored with the transmit FIFO buffer of the interprocessor communications interface corresponding to a particular processing subsystem, the associated control unit requests mastership of the interprocessor communications bus and transmit packet. The interprocessor communications interfaces of the remaining data processing subsystems decode the target information conveyed in the first byte of the transfer cycle. If the target information conveyed during a given transfer cycle corresponds to an assigned target value programmed for a particular interprocessor communications interface, that interprocessor communications interface operates a receiver.

REFERENCES:
patent: 4914653 (1990-04-01), Bishop et al.
patent: 5658005 (1997-08-01), Garde et al.

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