Electrical computers and digital processing systems: multicomput – Computer-to-computer direct memory accessing
Reexamination Certificate
2000-05-11
2004-01-13
Caldwell, Andrew (Department: 2157)
Electrical computers and digital processing systems: multicomput
Computer-to-computer direct memory accessing
C712S029000, C711S156000, C711S202000
Reexamination Certificate
active
06678722
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to an interprocessor communication system to realize a virtual memory for a parallel computer system, in which a plurality of processors is interconnected through a network.
Interprocessor communication is imperative for parallel processing through which plural processors process a single job. Here, the interprocessor communication refers to a data exchange between plural processors. The interprocessor communication is created in the course of the parallel processing between the plural processors to ensure proper cooperation between them. For this reason, the interprocessor communication is one of the overheads in the parallel processing. Accordingly, a high-speed performance of an interprocessor communication is unavoidably required to promote the effect of the parallel processing.
When plural users handle a computer system made up of parallel processors, it has been common to employ a so-called space-sharing method. In this method, the computer system is spatially divided in such a manner that the processors are individually allotted to each of the users to permit each processor to serve for each user and that a job in charge of each user is allowed to run exclusively in his allotted processors.
In this method, however, there is a limitation that the total number of processors which execute each user's job cannot surpass the number of the physical processors.
As one solution to overcome the above-described limitation and thereby to allow plural users to efficiently handle the computer system, the time-sharing method has been employed to time-share each of the parallel processors in the computer system.
In order to execute timesharing, however, support of a virtual memory will be essentially required. Here, the virtual memory refers to an external storage medium such as a hard disk to save the memory images of the jobs allocated to the plural users.
The reason for requirement for a virtual memory is as follows:
A promotion in performance capability of a processor has brought about a striking increase in a data size that a processor can handle for a calculation in the field of science and technology. In many cases, the distribution of data necessary for parallel processing is effected by first transmitting the data from a hard disk or a host machine to one of the processors (referred to as a first processor below), subsequently dividing the data into data sections in the first processor and distributing the data sections individually to the other processors. While the main memory of each processor other than the first processor stores a divided data section, the main memory of the first processor will be likely to overflow if the size of the data loaded from the hard disk or the host machine is too large. To solve this problem, it is imperative to support (to realize on software) a virtual storage capable of handling data of a data size that is larger than the capacity of the real main memory, using an external storage medium such as a hard disk.
In order to support a virtual memory in a parallel computer system, a problem encountered has been that speed-up of the interprocessor communication adversely results in a relative slow-down of the processing speed when paging-in a paged-out page from the disk to a main memory. This entails a temporary suspension of the interprocessor communication to wait for paging-in of the following page. The suspension of the interprocessor communication between certain two processors affects problematic influences on the interprocessor communications between other processors.
FIG. 1
is an explanatory diagram of page-in in a conventional parallel computer system: (A) represents a real memory with the entire area set up for page-in; (B) represents a real memory with a communication buffer allocated; and (C) represents a real memory with transmission area first paged-in on the transmission side and a reception area next paged-in on the receiver side through interprocessor communications. By the methods represented in
FIG. 1
, (A) to (C), even when the concerned processor breaks an interprocessor communication to carry out a page-in processing, such a break will not interfere with the communications between other processors as described below.
The traditional method
1
shown in
FIG. 1
, (A) gives a solution in which no virtual memory is employed. In this solution, it is not permitted to use any area within the main memory exclusively for the interprocessor communication. Thus, all the programs including the interprocess communication programs can be allocated to any area of the main memory and the page-out of the program from the main memory is prohibited. This solution entails the problem that the solution does not meet the above-described requirement of supporting the virtual memory for the parallel computer system.
The traditional method
2
shown in
FIG. 1
, (B) teaches a transmission buffer and a reception buffer for the interprocessor communication fixedly allocated on the transmission side and on the receiver side, respectively. In this method, data for an interprocessor communication is always communicated exclusively through the transmission buffer and a reception buffer. In other words, all steps of the interprocessor communication are carried out in a real-memory-to -real-memory scheme and no step for page-management between the main memory and a virtual memory intervenes in the process of the interprocessor communication. In this way, the interprocessor communication can be performed without interruption by the page management. However, a problem encountered in this method has been that the method requires the steps of copying data from a virtual memory to the transmission buffer before the interprocessor communication and also copying data from the reception buffer to a destination address after the interprocessor communication, with the two copy steps causing a degraded performance of the interprocessor communication.
In the traditional method
3
shown in
FIG. 1
, (C), a transmission area and a reception area are allocated beforehand every time interprocessor communication is intended. While data can be sent to the destination address without necessitating copying in this method, a problem encountered has been that additional steps of the interprocessor communication are required between the processors of concern to confirm the allocation of the data reception area in the real memory on the receiver side. These steps for confirmation substantially cause a degraded performance of the interprocessor communication, although the method requires no copy step.
The above-described traditional methods are summarized as follows: the traditional method
1
cannot support a virtual memory; in the traditional method
2
, the copying of data to the transmission buffer and the copying of data from the reception buffer to a destination address affect the interprocessor communication as an overhead that degrades significantly the performance of the interprocessor communication; and in the traditional method
3
, an additional interprocessor communication is needed to execute the confirmation procedures to confirm an allocation of the transmission area and the reception area to the real memories on the transmitter side and the receiver side, respectively. These confirmation procedures have to be carried out every time the interprocessor communication is intended even when the allocation of the transmission area and the reception area is maintained. The above-described additional interprocessor communication causes degradation in the performance of the interprocessor communication.
The present invention is intended to solve the above-described problems. In particular, the present invention is directed to minimizing the procedures that cause deterioration of the performance in the interprocessor communication when the memory areas associated with the interprocessor communication have been allocated to the real memory, thereby offering an interprocessor communication system having an i
Caldwell Andrew
NEC Corporation
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