Interprocessor communication

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Details

G06F 1336, G06F 1342

Patent

active

048071161

ABSTRACT:
In a multiprocessor system comprising a plurality of individual processor modules interconnected by a bus structure, including a bus controller, for providing communication between the processor modules, a method and apparatus for interprocessor communication includes one of the processor modules sending a request signal to the bus controller to request a transmission; the bus controller polling the processor modules to identify the requesting processor module; the requestor processor module responding to the poll with the identification of the receiver processor module; the bus controller interrogating the receiver processor module to determine its status (i.e., busy or available); and the bus controller then signaling transmission commencement.

REFERENCES:
patent: 3710324 (1973-01-01), Cohn et al.
patent: 3735365 (1973-05-01), Nakamura et al.
patent: 3810114 (1974-05-01), Yamada et al.
patent: 4038644 (1977-07-01), Duke et al.
patent: 4089052 (1978-05-01), Gruner

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