Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Wire contact – lead – or bond
Reexamination Certificate
2000-01-06
2002-08-06
Lee, Eddie (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Wire contact, lead, or bond
C257S700000, C257S692000, C257S695000, C257S672000, C257S676000
Reexamination Certificate
active
06429534
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates generally to semiconductor chip device packages and assembly. More specifically, the invention relates to an interposer tape for a tape ball grid array package which permits varying sized dies to be used for the same package.
In semiconductor design and assembly, an integrated circuit chip or “die” may be bonded to a tape substrate before connection to a board.
FIG. 1A
illustrates a conventional tape ball grid array (TBGA) package
100
. The conventional TBGA package
100
has a die
102
mounted upon a tape
104
. The tape
104
includes bond fingers
106
for wire bonding to bond pads
107
of the die
102
. The bond fingers
106
are connected to ball attach sites
108
via connecting metal traces
110
(FIG.
1
B). The ball attach sites
108
coincide with holes
112
which are used for attaching solder balls to the conventional TBGA package
100
. The solder balls permit external communication, i.e. to a mother board.
Often, it is desirable to change the size of the die
102
for the conventional TBGA package
100
. For the tape
104
, the size of the die
102
is limited to a range of sizes. For smaller dies, this limitation is determined by the length of bond wires
112
which extend from the die
102
to the bond fingers
106
. More specifically, during injection of an encapsulating plastic, long bond wires
112
are likely to bend, contact each other and short out. This phenomenon is known as “sweep” and limits the length of bond wires
112
. As a result, to substantially decrease the size of the die
102
, a new tape
104
is typically required.
The metal traces
110
, the bond fingers
106
and the ball attach sites
108
form an interconnect pattern
111
as illustrated in FIG.
1
B. In the past, to overcome sweep and permit a smaller die
102
, designers have opted to alter the interconnect pattern
111
. One. interconnect pattern
111
approach has been to move the bond fingers
106
towards the die
102
. However, this solution is limited by the width of the metal traces
110
and the. density of the interconnect pattern
111
. More specifically, conventional routing limitations dictate that a maximum of three or less metal traces
110
may be placed between two adjacent ball attach sites
108
. More than three metal traces
110
placed between two adjacent ball attach sites
108
may compromise the mechanical strength and manufacturability of the tape
104
. As a result, the bond fingers
106
may not extend close enough to the die
102
to allow manageable wire bond lengths to connect to the bond pads
107
. Correspondingly, the size of the die
102
remains limited for the tape
104
.
Thus, the length of the wire bonds
112
and the interconnect pattern
111
limit the size of the die
102
which can be used for the tape
104
. If the die
102
size is changed, such that it is outside the range of the bond wires
112
, a new tape must be designed and manufactured. As a result, this requires the design of multiple tapes for different die sizes. Each new tape increases cost and time consumption in design and manufacturing. In addition, it also quite common that different size dies also change the interconnect pattern
111
, which necessitates a new tape and increases costs for the package
100
. Further, in some cases, the allowable wire length for the wire bonds
112
and interconnect pattern
111
routability may limit the minimum size of the die
102
.
In view of the foregoing, a package which may accommodate multiple die sizes and small die sizes would be desirable.
SUMMARY OF THE INVENTION
To achieve the foregoing, the present invention provides an interposer tape which provides electrical communication between a die and a packaging substrate. The interposer tape permits multiple die sizes to be used for the substrate. More specifically, the dimensions of the interposer tape may vary to accommodate a variety of die sizes for the substrate. The interposer tape includes an array of traces. The array of traces provide electrical communication between bond pads of the die and bond fingers of the substrate. A first set of wire bonds may be formed between the array of traces and the bond pads of the die. A second set of wire bonds may be formed between the array of traces and the bond fingers of the substrate.
In one aspect, the invention provides a semiconductor package. The semiconductor package includes a packaging substrate. The semiconductor package also includes an interposer tape mechanically bound to the packaging substrate and in electrical communication with the packaging substrate. The semiconductor package further includes a die mechanically bound to the substrate and in electrical communication with the interposer tape, wherein the interposer tape provides electrical communication between the substrate and the die.
In another aspect, the invention relates to an interface between a die and a packaging substrate. The interface includes an interface substrate. The interface also includes an array of conductive links, wherein the array of conductive links are adapted to fitting a plurality of die sizes to the packaging substrate.
In yet another aspect, the invention provides a method of fabricating a semiconductor package. The method includes providing a packaging substrate. The method also includes mechanically binding an interposer tape to the substrate, the interposer tape including an array of conductive links. The method further includes mechanically binding a die to the substrate. The method additionally includes forming a first set of wire bonds between the interposer tape and the die. The method also includes forming a second set of wire bonds between the interposer tape and the substrate.
These and other features and advantages of the present invention are described below with reference to the drawings.
REFERENCES:
patent: 5138430 (1992-08-01), Gow, 3rd et al.
patent: 5168345 (1992-12-01), Brossart
patent: 5332864 (1994-07-01), Liang et al.
patent: 5468681 (1995-11-01), Pasch
patent: 5569956 (1996-10-01), Chillara et al.
patent: 5646829 (1997-07-01), Sota
patent: 6124546 (2000-09-01), Hayward et al.
Alagaratnam Maniam
Chia Chok J.
Low Qwai H.
Beyer Weaver & Thomas LLP
Fenty Jesse A.
Lee Eddie
LSI Logic Corporation
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