Interposer substrate with low inductance capacitive paths

Details Interposer substrate with low inductance capacitive paths Interposer substrate with low inductance capacitive paths

2001-10-03

2002-11-05

Dinkins, Anthony (Department: 2831)

Electricity: electrical systems and devices

Electrostatic capacitors

Fixed capacitor

C361S763000, C361S306100

Reexamination Certificate

active

06477034

ABSTRACT:

FIELD OF THE INVENTION
The present invention pertains to integrated circuit device packaging, and in particular, to interposer substrates for mounting integrated circuit die, and more particularly to interposer substrates that provide capacitance and methods of making the same.
BACKGROUND OF THE INVENTION
It is desirable to provide decoupling capacitance in close proximity to integrated circuit (IC) die, and the need for such capacitance increases as the switching speed and current requirements of the devices becomes higher. For example, current microprocessor die have switching speeds that exceed 1 GHz and have high current demand. To help provide this needed capacitance, discrete capacitors have been mounted as separate components on the surface of the substrate next to the IC die. However, this arrangement uses up valuable “real estate” on the surface of the substrate and suffers from the fact that such discrete capacitors are not as close to the IC die as needed resulting in unacceptable inductance. In some designs, decoupling capacitance is incorporated into multilayered substrates by forming capacitor plates within the substrate. This technique adds complexity to the multilayered substrate, reducing the manufacturing yield. In such designs, the capacitor structure is one of the most likely components to be defective due to the relatively close spacing of the plates and the possibility of pin-hole defects or other causes of electrical shorting or leakage in the thin dielectric layer between the plates. If a defective capacitor is incorporated into a substrate, such as a multichip module (MCM) substrate, and the defect is not discovered until fabrication of the substrate is complete, the resulting loss may be quite significant.
Another problem with traditional approaches to packaging IC die is the method used for delivering power to the die. Power lines are generally routed through the same substrate utilized to carry signals to and from the die. Equally important is the fact that the thinness of the substrates results in power feeds to the IC die that have relatively high impedance. This high impedance results in undesired noise, power loss and excess thermal energy production. These same problems are applicable to routing power and signal lines though an interposer substrate. Such interposer substrates are mounted on a base substrate, with the IC die being mounted on the interposer substrates.
Thus, there is general need for apparatus that reduce the inductance and improve the capacitance on power supply lines for IC die. There is also a general need for a decoupling capacitor that may be used as an interposer substrate between a die and an organic substrate. Thus, there is also a need for a high-performance decoupling array capacitor structure that may be used as an interposer substrate between a die and an organic substrate. Thus, there is also a need for an interposer substrate that reduces a coefficient of thermal expansion mismatch between a die and an organic substrate. Thus, there is also a need for an interposer substrate that provides reduced inductance and improved capacitance between a die and an organic substrate. Thus, there is also a general need for delivering power to a die with reduced inductance.


REFERENCES:
patent: 5774326 (1998-06-01), McConnelee et al.
patent: 5786238 (1998-07-01), Pai et al.
patent: 6034332 (2000-03-01), Moresco et al.
patent: 6102710 (2000-08-01), Beilin et al.
patent: 6184476 (2001-02-01), Takahashi et al.
patent: 6195249 (2001-02-01), Honda et al.

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