Electricity: conductors and insulators – Conduits – cables or conductors – Preformed panel circuit arrangement
Reexamination Certificate
2000-02-08
2002-01-01
Paladini, Albert W. (Department: 2841)
Electricity: conductors and insulators
Conduits, cables or conductors
Preformed panel circuit arrangement
C174S261000, C174S262000, C361S760000, C257S686000, C257S738000, C257S778000
Reexamination Certificate
active
06335491
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates generally to semiconductor chip packages and assembly. More specifically, the invention relates to an interposer which improves the performance reliability of a package and permits larger substrates and higher pin counts.
In semiconductor device assembly, a package is typically attached to a board.
FIG. 1A
illustrates a conventional semiconductor device
100
which includes a package
102
attached to a printed circuit board
104
. The package
102
includes a die
106
mounted upon a substrate
108
. The substrate
108
includes bond pads
110
for receiving solder balls
112
which permit electrical communication between the substrate
108
and the die
106
. The substrate
108
is mounted on the printed circuit board
104
using solder balls
114
at landings
116
included on the printed circuit board
104
. The solder balls
114
provide electrical communication and mechanical attachment between the substrate
108
and the board
104
. The distance between solder balls
114
is referred to as the solder ball pitch
120
.
In the current semiconductor environment, a die is continually being called upon to sustain an increasing number of functions. As die complexity continues to increase, including applications having multiple functions, I/O communication with the die
106
must also suitably increase. The number of I/O connections between the substrate
108
and the die
106
, or the substrate
108
and the board
104
, is referred to as a ‘pin count’. Designers are presently calling for pin counts in the range of up to two thousand pins. Current pin counts are limited by the size of the substrate
108
and the pitch
120
. For the semiconductor device
100
, the current substrate
108
size limit is 32 mm square and the current pitch
120
limit is 1.27 mm, resulting in a current pin count limit of 625 pins.
The size of the substrate
108
is currently limited by thermal performance considerations. More specifically, differences in the coefficients of thermal expansion between the die
106
, the substrate
108
and the board
104
lead to differential expansion and contraction of these components during thermal cycling. This differential thermal strain creates substantial stress upon the solder balls
112
and the solder balls
114
, which are fixed. By way of example, the substrate
108
may be comprised of a ceramic material having a coefficient of thermal expansion in the range of 6 parts per million (PPM). The board
104
may be comprised of a resin based material having a coefficient of thermal expansion in the range of 18 PPM. As the device
100
is expected to undergo constant thermal cycling during its operational lifetime, the thermal expansion differences between the substrate
108
and the board
104
may create substantial stress in the solder balls
114
. This thermal strain-induced stress may cause the solder balls
114
to crack or lose contact, thereby compromising performance of the semiconductor device
100
.
For the die
106
, the substrate
108
and the board
104
, the neutral point of thermal expansion is typically in the center of each component. As distance from the neutral point increases, thermal expansion effects increase. In other words, as distance from the neutral point increases, more pronounced are the effects of thermal strain-induced stress upon the solder balls
114
between the substrate
108
and the board
104
. The stress upon the solder balls
114
at the periphery of the substrate
108
often limits the substrate
108
size. Thus, the substrate
108
size and pin count are limited by a thermal performance mismatch between the substrate
108
and the board
104
.
Similar thermal performance difference problems exist for the solder balls
112
between the substrate
108
and the die
106
. By way of example, the die
106
is typically comprised of silicon having a coefficient of thermal expansion in the range of 2-4 PPM. Although the distances from the furthest solder balls
112
to the neutral point for the substrate
108
are not as large as that for the solder balls
114
between the substrate
108
and the board
104
, the thermal expansion and contraction differences between the substrate
108
and the die
106
may still compromise performance of the device
100
. Thus, the substrate
108
size and pin count are further limited by thermal performance differences between the die
106
and the substrate
108
.
One conventional solution to address the thermal performance differences between the substrate
108
and the board
104
is the use of solder columns in place of solder balls.
FIG. 1B
illustrates a ceramic column grid array (CCGA)
130
including columns
132
which extend from a substrate
134
to a printed circuit board
136
. The CCGA
130
increases the height between the substrate
134
and the board
136
to about 100 mils from the conventional 30 mils of FIG.
1
A. By increasing the height of the connection, the compliance of the connection between the substrate
134
and the board
136
is increased. This increased compliance results in lower stresses for peripheral columns and thus permits a larger substrate
134
, and more columns
132
.
While the CCGA
130
permits a substrate size up to a maximum of 44 mm square and a pin count in the range of 1600-1700 pins, there are several problems with this design. Firstly, the geometry of the columns introduces fragility to the CCGA
130
. As a result, extensive care must be taken while handling the CCGA
130
at the risk of fracturing one or more columns
132
. As the CCGA
130
is often shipped in component form to various manufacturers, this fragility represents an obstacle to CCGA
130
acceptability. Secondly, as mentioned before, pin count requirements in some desired applications are in range of 2000 pins, which is outside the allowable limit of the CCGA
130
. Thus, the CCGA
130
is not suitable for increasing I/O demands of modern semiconductor devices.
In view of the foregoing, a semiconductor device which may improve thermal performance differences between its components would be desirable. In addition, a semiconductor device which may accommodate increased pin counts would also be desirable.
SUMMARY OF THE INVENTION
To achieve the foregoing, the present invention describes an interposer which improves the thermal performance of a semiconductor device. The interposer may be situated between a substrate and a board. The interposer is attached to two layers of solder balls. The first layer of solder balls electrically and mechanically connects the interposer to the substrate. The second layer of solder balls electrically and mechanically connects the interposer to the board. In one aspect, the coefficient of thermal expansion (CTE) of the interposer may be flexibly selected to reduce thermal strain-induced stress for either or both layers of solder balls resulting from thermal performance differences between the substrate and the interposer or the interposer and the board. In another aspect, the CTE of the interposer may be reduced to allow a lower CTE for the substrate, which in turn may reduce thermal strain-induced stress for solder balls between the substrate and a die attached to the substrate. Advantageously, the improved thermal performance of the present invention may allow larger substrates, larger dies, larger solder ball arrays, reduced solder ball pitches and pin counts well above conventional levels without compromising semiconductor device reliability.
In addition to improving thermal performance, the interposer also improves compliance of the semiconductor device to permit larger substrates and increased pin counts. The addition of the interposer to the semiconductor device increases the height between the substrate and the board. By increasing the height, compliance between the substrate and the board is increased. This increased compliance results in lower stresses for peripheral solder balls and thus permit larger solder ball arrays, larger substrates and increased pin counts. The second lay
Alagaratnam Maniam
Desai Kishor V.
Patel Sunil A.
Beyer Weaver & Thomas LLP
LSI Logic Corporation
Paladini Albert W.
Patel I B
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