Electrical connectors – Preformed panel circuit arrangement – e.g. – pcb – icm – dip,... – With provision to conduct electricity from panel circuit to...
Reexamination Certificate
2000-04-03
2002-04-30
Luebke, Renee (Department: 2833)
Electrical connectors
Preformed panel circuit arrangement, e.g., pcb, icm, dip,...
With provision to conduct electricity from panel circuit to...
C029S852000, C029S842000, C029S846000
Reexamination Certificate
active
06379159
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to technology of an interposer for a chip size package which is interposed between a semiconductor device and a circuit board for electric connection therebetween when the semiconductor device is packaged on the circuit board.
The present application is based on Japanese Patent Applications No. Hei. 11-96918 and 11-224221, which is incorporated herein by reference.
2. Description of the Related Art
Generally, a large number of semiconductor devices such as ICs are formed on a wafer, and separated into individual chips which are connected to several kinds of circuit boards. Further large-scale integration of an IC increases the number of electrodes formed on a single chip so that the shape of each electrode and the array pattern is fine and provide a narrow pitch. In the field of packaging technology, a method (e.g. flip-chip bonding) has been proposed which does not use wire bridging between a chip and a circuit board, but use correlative connecting between the electrode position of the chip and conductor portion of the circuit board. In order to satisfy the requirement of miniaturization, a bare chip packaging in which the chip is packaged in an naked state has been proposed.
In recent years, in accordance with the above requirement, a “chip size package” (CSP) has been proposed which packages the chip on a circuit board with its size being maintained to occupy a much smaller area than a conventional package does. The CSP achieves the packaging of the chip size by interposing a flexible circuit board (called “interposer”)
20
equipped with a contact between a chip
30
and an external circuit board
40
for their interconnection as shown in FIG.
7
A. The circuit board may be various kinds such as a circuit board for packaging or a general circuit board on which a large number of elements are also packaged.
As shown in
FIG. 7A
, the interposer
20
includes a circuit pattern
22
within an insulating substrate
21
(which actually has a laminated structure) which has a size approximately equal to or slightly larger than the chip
30
. The interposer
20
has also a contact
23
in the insulating substrate
21
on the side of the chip
30
at the position which individually corresponds to the electrode pad (not shown) of the chip. The interposer has also a contact
24
in the insulating substrate
21
on the side of the circuit board at the position which corresponds to the pad of the circuit formed on the circuit board. These contacts
23
and
24
are formed in various manners of a bump, a flat form in flush with the substrate surface, etc. These large number of contacts
23
and
24
lead to the internal circuit pattern
22
. In this way, the individual electrodes of the chip is connected to the circuit
41
of the circuit board
40
through the contact
23
, circuit pattern
22
and contact
24
of the interposer
20
.
However, the contacts formed in the conventional interposer have greatly different heights with respect to the surface of the insulating substrate
21
. Now, the “height” refers to the height of the contact which is not only projected from the substrate surface but also dented therefrom. Because of such height difference, some of the contacts cannot be in contact with the electrodes formed on the rigid chip
30
. This gives rise to a problem in reliability of connection.
In the example shown in
FIG. 7B
, a contact
23
b,
which is located between the surrounding contacts
23
a
and
23
c
and has a projecting height lower than them by a distance y, cannot be brought into contact with the chip
30
. If the projecting height of the pertinent contact is slightly lower than that of the surrounding contacts, it is apparently in contact with the chip. However, its contact area is smaller by the degree of reduction of a crushing margin when it is brought into contact. This cannot provide good reliability in connection.
Since the interposer
20
is interposed between the chip
30
and the circuit board
40
, the above problem in connection between the interposer
20
and the chip
30
occurs also in connection between the interposer
20
and the circuit board
40
. Specifically, as understood by replacing the chip
30
by the circuit board
40
, the contact which is lower by y in its projecting height than the surrounding contacts cannot be brought into contact with the conductor portion of the circuit board.
SUMMARY OF THE INVENTION
A primary object of the present invention is to solve the above problems occurring in connection between the interposer and the chip and between the interposer and the circuit board.
Another object of the present invention is to provide a method of manufacturing an interposer for CSP which can reduce a difference in the height among contacts with respect to a surface of an insulating substrate.
Still another object of the present invention is to provide a preferable interposer for CSP and its intermediate member which can be obtained by the above manufacturing method.
The method for manufacturing an interposer for CSP according to the present invention, interposer itself and its intermediate body have the following aspects or features.
(1) A method for manufacturing an interposer for a chip size package, comprising:
a first step of forming a first insulating layer on a substrate which is made of metal and usable as a cathode for electroplating;
a second step of forming a first opening at a position of the insulating layer corresponding to a conductor portion of an object for connection so that a surface of the substrate is exposed to an inner bottom of the opening;
a third step of filling the first opening with metal by electroplating using the substrate as a cathode, thereby forming a conductive path in the first opening;
a fourth step of forming a circuit pattern in contact with the conductive path on the first insulating layer; and
a fifth step of removing the substrate partially or entirely to expose the first insulating layer inclusive of an end surface of the conductive path.
(2) A method for manufacturing an interposer according to the aspect (1), wherein the conductor portion of the object for connection is an electrode of a chip.
(3) A method for manufacturing an interposer according to the aspect (1), wherein the conductor portion of the object for connection is a conductor portion of a circuit board.
(4) A method for manufacturing an interposer according to the aspect (1) or (2), wherein the first insulating layer is made of photosensitive and thermal melting type adhesive resin.
(5) A method for manufacturing an interposer according to the aspect (1), further, after the fourth step, comprising the step of:
forming a second insulating layer so as to cover the circuit pattern and forming a second opening from which the circuit pattern is exposed.
(6) A method for manufacturing an interposer according to the aspect (1), wherein the conductor portion of the object for connection is a conductor portion of a circuit board, further comprising, after the fourth step, the step of:
forming a second insulating layer so as to cover the circuit pattern and forming a second opening exposing the circuit pattern at a position of an electrode of a chip which is the object for connection, and filling the second opening with metal.
(7) A method for manufacturing an interposer according to the aspect (6), wherein the first insulating layer is made of photosensitive resin, and the second insulating layer is made of photosensitive and thermal melting type adhesive resin.
(8) A method for manufacturing an interposer according to the aspect (1), wherein in the fifth step, the substrate for a cathode is removed to be left as a frame for supporting the interposer on its periphery.
(9) A method for manufacturing an interposer according to the aspect (1), wherein the substrate has an outer size enough to arrange a plurality of interposers for a chip size package, and the plurality of interposers which are collected on the substrate in a state where they can be separ
Fujii Hirofumi
Mune Kazunori
Ouchi Kazuo
Tanigawa Satoshi
Hammond Briggitte R.
Luebke Renee
Nitto Denko Corporation
Sughrue & Mion, PLLC
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