Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor
Patent
1997-09-17
1999-10-26
Niebling, John F.
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
438127, H01L 2144, H01L 2148, H01L 2150
Patent
active
059727349
ABSTRACT:
A ball grid array package (BGA) according to the present invention has an interposer between a bond pad on the lower surface of the substrate and the solder ball. The interposer has a conductive portion in contact with the bond pad surrounded by a nonconductive or insulating portion. The conductive portion in contact with the bond pad is sufficiently constrained from widening during a subsequent reflow process by the presence of the nonconductive or insulating portion. The contact with the bond pad is sufficiently small to allow traces to pass near the bond pad substantially directly en route to another bond pad. The nonconductive portion also prevents subsequently-applied encapsulant from coming in contact with and contaminating the bond pad. The elevated surface of the interposer, i.e. the surface of the interposer furthest from the bond pad, supports the solder ball, and is sufficiently wide to support the solder ball without allowing the solder ball to come in contact with the traces. The solder ball and the trace routing on the lower surface of the substrate is in different planes, thereby allowing a simplified trace routing, but retaining and even increasing rigidity of the structure and coplanarity of the solder balls.
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Carichner Karla Y.
Liang Dexin
Jones Josetta
LSI Logic Corporation
Niebling John F.
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