Interposer containing bypass capacitors for reducing voltage...

Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Multiple housings

Reexamination Certificate

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Details

C257S691000, C257S724000, C257S738000, C257S777000, C257S778000

Reexamination Certificate

active

10871845

ABSTRACT:
One embodiment of the present invention provides an apparatus that reduces voltage noise for an integrated circuit (IC) device. This apparatus includes an interposer, which is configured to be sandwiched between the IC device and a circuit board. This interposer has a bottom surface, which is configured to receive electrical connections for power, ground and other signals from the circuit board, and a top surface, which is configured to provide electrical connections for power, ground and the other signals to the IC device. A plurality of bypass capacitors are integrated into the interposer and are coupled between the power and ground connections for the IC device, so that the plurality of bypass capacitors reduce voltage noise between the power and ground connections for the IC device.

REFERENCES:
patent: 6961230 (2005-11-01), Otsuka et al.
patent: 6970362 (2005-11-01), Chakravorty
patent: 2003/0102555 (2003-06-01), Patel et al.

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