Interpolator based clock and data recovery (CDR) circuit...

Details Interpolator based clock and data recovery (CDR) circuit... Interpolator based clock and data recovery (CDR) circuit...

2008-01-01

2008-01-01

Deppe, Betsy L. (Department: 2611)

Pulse or digital communications

Synchronizers

Synchronizing the sampling time of digital data

Reexamination Certificate

active

10781099

ABSTRACT:
The present invention facilitates clock and data recovery (330,716/718) for serial data streams (317,715) by providing a mechanism that can be employed to maintain a fixed tracking capability of an interpolator based CDR circuit (300,700) at multiple data rates (e.g.,800). The present invention further provides a wide data rate range CDR circuit (300,700), yet uses an interpolator design optimized for a fixed frequency. The invention employs a rate programmable divider circuit (606,656,706) that operates over a wide range of clock and data rates (e.g.,800) to provide various phase correction step sizes (e.g.,800) at a fixed VCO clock frequency. The divider (606,656,706) and a finite state machine (FSM) (612,662,712) of the exemplary CDR circuit (600,650,700) are manually programmed based on the data rate (614,667). Alternately, the data rate may be detected from a recovered serial data stream (718) during CDR operations (on-the-fly) utilizing a frequency detection circuit (725) to automatically program the divider (706) and FSM (712) to provide CDR circuit operation at the nearest base clock rate (716).

REFERENCES:
patent: 6114914 (2000-09-01), Mar
patent: 6901126 (2005-05-01), Gu
patent: 7079615 (2006-07-01), Bailey
patent: 7162002 (2007-01-01), Chen et al.
patent: 2002/0131539 (2002-09-01), Li et al.
patent: 2003/0212930 (2003-11-01), Aung et al.

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