Coded data generation or conversion – Digital pattern reading type converter – Optical
Reexamination Certificate
2003-12-18
2004-11-09
Jeanglaude, Jean Bruner (Department: 2819)
Coded data generation or conversion
Digital pattern reading type converter
Optical
C250S231130
Reexamination Certificate
active
06816091
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to optical encoders.
BACKGROUND OF THE INVENTION
Optical encoders provide a readout of the position of an apparatus relative to a predetermined location. For example, an absolute shaft encoder provides a readout of the number of degrees through which the shaft has rotated since a predetermined fiducial mark was detected. An incremental encoder provides a signal each time the shaft rotates a predetermined number of degrees. Linear analogs of the above-described shaft encoder function in a similar manner.
To simplify the following discussion, the present invention will be explained in terms of a shaft encoder; however, the principles of the present invention can be applied to other forms of encoders.
Typically, a shaft encoder utilizes a code wheel having a series of light and dark strips that modulate a light source. The light from the code strip is viewed by one or more photodetectors. Typically, four detectors intercept the light signals generated by one dark and one light strip. These detectors process the light signals to provide a resolution of one half the width of a stripe. That is, the encoder provides a signal having four states that divide one dark and one light stripe into four regions. To improve the resolution of such an encoder; one must increase the number of stripes around the code wheel and decrease the size of the detectors. There is, however, a minimum size for the detectors and code strips which imposes limitation on the resolution that can be achieved by miniaturizing the code strips and detectors.
One method for improving the resolution of the encoder without shrinking the size of the code strips and detectors is to provide an interpolator that effectively divides the stripes into smaller regions. For example, U.S. Pat. No. 6,355,927 describes such an interpolator. To provide an interpolation factor of n, this invention requires a processing circuit having 2n comparators. For large values on n, the costs associated with the interpolator become significant.
SUMMARY OF THE INVENTION
The present invention includes an interpolation circuit and method for interpolating a signal. The interpolation encoder includes a circuit that generates out-of-phase ramp signals and the complements of those ramp signals. A fractional signal circuit generates one or more fractional ramp signals from the out-of-phase ramp signals. The interpolation circuit utilizes first and second comparators to compare various ones of the ramp signals and fractional ramp signals. Each comparator includes a first input and a second input and generates a comparator output signal indicative of whether the first input is greater than the second input. The interpolator utilizes first, second, third and fourth multiplexers to select which ramp signals form the inputs of the comparators. Each multiplexer has multiplexer inputs that include the ramp signals and the fractional ramp signals. Each multiplexer couples its multiplexer in puts to a corresponding input of the first comparator or of the second comparator. The input is determined by a multiplexer control signal coupled to that multiplexer. A finite state machine having state inputs that include the comparator output signals and a current state signal that indicates one of a plurality of states determines the multiplexer control signals. The finite state machine generates a next state signal from the state inputs. The current state signal is replaced by the next state signal in response to a clock signal.
One embodiment also includes a first circuit for generating the ramp signal from the first and second out-of-phase channel signals that define N states and a second circuit for generating third and fourth out-of-phase channel signals from the current state signal, the third and fourth channel signal defining M states where M>N. The fractional ramp signals can be generated by a fractional signal circuit that includes a multiplexer having multiplexer inputs that include the ramp signals and a scaling amplifier having a scaling circuit input connected to the multiplexer output. The ramp signal that is scaled at any given time being determined by the current state signal. In one embodiment, the finite state machine detects a startup condition and determines a startup state from the outputs of the comparators when selected current state signals are generated.
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Glenn (US Application No. 10/039,374; Pgpub 2003/0122588) “Voltage controller for a highly linear phase interpolator”, filed on Jan. 2, 2002.
Agilent Technologie,s Inc.
Jeanglaude Jean Bruner
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