Electrical computers: arithmetic processing and calculating – Electrical analog calculating computer – Particular function performed
Reexamination Certificate
2003-10-07
2008-08-12
Ngo, Chuong D (Department: 2193)
Electrical computers: arithmetic processing and calculating
Electrical analog calculating computer
Particular function performed
C708S290000, C327S231000
Reexamination Certificate
active
07412477
ABSTRACT:
Method and apparatus for interpolation of signals from a delay line is described. An input signal is obtained from which progressively delayed input signals are generated from the input signal. Two of the progressively delayed input signals are accessed and interpolated to provide a phase-adjusted signal.
REFERENCES:
patent: 6204733 (2001-03-01), Cai
patent: 6396360 (2002-05-01), Cai
patent: 2002/0021775 (2002-02-01), Dietl et al.
patent: 2002/0113637 (2002-08-01), Huang et al.
Lee, Thomas H. et al.; “A 2.5 V CMOS Delay-Locked Loop for an 18 Mbit, 500 Megabytes/s DRAM”; IEEE Journal of Solid-State Circuits, vol. 29, No. 12, Dec. 1994; pp. 1491-1496.
Maneatis, John G.; “Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques”; IEEE Journal of Solid-State Circuits, vol. 31, No. 11, Nov. 1996; pp. 1723-1732.
Sidiropoulos, Stafanos; “A Semidigital Dual Delay-Locked Loop”; IEEE Journal of Solid-State Circuits, vol. 32, No. 11, Nov. 1997; pp. 1683-1692.
Bult, Klaas et al.; An Embedded 240-mW 10-b 50-MS/s CMOS ADC in 1-mm2; IEEE Journal of Solid-State Circuits, vol. 32, No. 12, Dec. 1997, pp. 1887-1895.
Chou, ju-Ming et al.; “A 125MHz 8b Digital-to-Phase Converter”; ISSCC 2003 / Session 24 / Clock Generation / Paper 24.8; two pages.
Hardaway Michael R.
Ngo Chuong D
Webostad E. Eric
Xilinx , Inc.
LandOfFree
Interpolation of signals from a delay line does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Interpolation of signals from a delay line, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Interpolation of signals from a delay line will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4012487