Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
1998-06-12
2001-08-14
Ngo, Chuong Dinh (Department: 2121)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
C708S316000
Reexamination Certificate
active
06275836
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a telecommunications system which can perform digital-to-analog (“D/A”) conversion, or to an interpolation filter which can switch between integer and fractional interpolation rates to accommodate a fixed oversampling output rate for differing digital signal input frequencies.
2. Description of the Related Art
Mixed signal integrated circuits are generally well known as those which operate on both analog and digital signals. Such an integrated circuit may include analog-to-digital (“A/D”), D/A and digital signal processing (DSP) functions on a single monolithic substrate.
There are numerous types of mixed signal integrated circuits. One popular example involves a CODEC. Generally speaking, a CODEC may involve manipulating both analog and digital signals useful in the telecommunications field. An analog input signal is generally converted to a digital format, where multiple real-time operations can be readily performed on the digital signal before transmitting the digital signal onto a transmission medium. The CODEC can further include a mechanism for receiving digital signals from the transmission medium and converting those received signals to an analog format. Thus, encoding into a digital format and decoding from the digital format allows DSP operations to be performed using rapid digital operations. Operations such as multiplication, summing and delay can occur in succession on the digital signals before and after they are transmitted to enhance their transmissivity. These elemental operations an be performed many times for each sample of the incoming signal.
FIG. 1
is a block diagram of a CODEC
10
, according to one conventional form. CODEC
10
includes an amplifier
12
having gains sufficient to forward an analog input signal A
IN
to an encoder
14
. Encoder
14
may include many operational blocks which convert the analog input signal to a digital bit stream with minimum noise induced within the passband of interest. A popular A/D converter includes oversampled converters, or delta-sigma converters. Essentially, a delta-sigma converter digitizes an analog signal at a very high sampling rate (i.e., oversampling) to perform a noise-shaping function. Digital filtering after noise-shaping allows the delta-sigma converter to achieve a higher effective resolution than the analog input signal. Decimation can be used to reduce the oversampling data rate back to the original “Nyquist” rate.
The Nyquist data rate of the digital bit stream D
OUT
can be forwarded to a transmitter
16
as shown. Transmitter
16
as well as receiver
18
are situated near ports of CODEC
10
to transmit and receive respective digital signals through a channel
20
operably linked to CODEC
10
. Similar to transmitter
16
, receiver
18
may include amplification and/or error correction circuitry which operates solely within the digital domain. Resulting from receiver
18
is a digital bit stream D
IN
forwarded to a decoder
22
. The analog output from decoder
22
can thereafter be amplified by amplifier
24
and presented back as an analog output signal A
OUT
. Similar to encoder
14
, decoder
22
includes a delta-sigma converter and a digital filter. However, instead of using the delta-sigma converter as an A/D converter followed by a digital decimation filter, decoder
22
is configured with an interpolation filter coupled to receive the digital input D
IN
prior to performing D/A conversion which uses, in part, a delta-sigma modulator.
FIG. 2
illustrates in more detail an exemplary set of blocks which may be used to form decoder
22
. Several bit lines of a digital word can be fed as D
IN
to an interpolation filter
24
. The data rate of each digital word is shown at frequency fs. Interpolation filter
24
includes a sampling rate conversion switch which increases the sampling rate of the incoming bit stream D
IN
from fs to a higher sampling rate Fs. The technique of sample rate conversion used in interpolation or decimation is generally well known. Included with sample rate conversion may be a filter transfer function carried out by operations performed by the DSP portion of the mixed signal integrated circuit. An execution unit which performs a summing, delay and/or multiplication operation can be used to implement any filter transfer function.
Delta-sigma modulator
26
within decoder
22
proves useful in noise-shaping the high data rate bit streams and may also serve to reduce a multi-bit digital word to a single sample width of one bit. Unlike a delta-sigma modulator within an A/D block, modulator
26
exclusively performs digital operations. The transfer function is implemented in the digital domain possibly with an infinite impulse response (“IIR”) filter. The transfer function filtering operation performs the same modulator function as the A/D unit, where the in-band noise is suppressed but induces higher frequency quantization noise.
Output from delta-sigma modulator
26
can be fed as a single bit data stream transitioning at a relatively high rate Fs into a one bit D/A converter
28
, and the output of converter
28
is filtered in the analog domain by smoothing filter
30
. Smoothing filter
30
helps remove the shaped quantitization noise induced by modulator
26
, and rejects any images which result above the output Nyquist rate fs.
A mixed signal integrated circuit is shown in
FIGS. 1 and 2
to involve not only a mechanism to form a digital signal, but also recover analog information from that digital signal using an interpolation filter
24
, followed by a delta-sigma modulator
26
. The interpolation filter
24
thereby forms part of a transmission system and, more particularly, part of a D/A converter (or decoder). The multi-bit word line of interpolation filter
24
can receive a bit stream of varying data rate (i.e., frequency) depending on the telecommunications application. For example, the transmission system and particularly the CODEC can be called upon to send either data or voice information. This implies that the incoming data stream D
IN
can have a wide variety of frequencies fs depending on the transmitter/receiver constraints as well as the transmission medium. A variety of frequencies fs can also arise depending on the transmission system used and/or the transmission application desired. For example, modem applications involving data transmissions may utilize different frequencies fs than audio applications involving voice. However, to maintain compatibility with an existing (fixed) modulator
26
and D/A converters
28
, the data rate Fs should remain consistent when changing from one input frequency fs to the next. This will enhance applicability of an existing D/A converter to many different input frequencies.
A need, therefore, exists for having an interpolation filter which can accommodate varying baseband sampling frequencies fs, and can interpolate those varying frequencies to a fixed oversampling frequency Fs for use by a delta-sigma modulator operating at a fixed sampling rate. The desirable interpolation filter would thereafter enhance applicability of existing D/A converters to many different input frequencies. In order to accommodate a wide variety of input frequencies fs, the desired interpolation filter must not only involve a programmable interpolation rate, but also must be capable of selecting between fractional and integer interpolation rates on-the-fly.
SUMMARY OF THE INVENTION
The problems outlined above are in large part solved by an improved interpolation filter hereof. The interpolation filter can accommodate an incoming signal transitioning at varying sample rates fs. If the sample rate should change, the interpolation filter will modify its interpolation rate to maintain a constant and fixed oversampling output data rate Fs. The oversampling output can be maintained even if the interpolation rate involves switching between an integer and fractional interpolation ratio. In this manner, the interpolation filter used within the D/A converter can accom
Conley & Rose & Tayon P.C.
Daffer Kevin L.
Ngo Chuong Dinh
Oak Technology, Inc.
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