Interpolation-decimation circuit for increasing or decreasing di

Details Interpolation-decimation circuit for increasing or decreasing di Interpolation-decimation circuit for increasing or decreasing di

1975-09-24

1977-04-26

Malzahn, David H.

Registers

Transfer mechanism

Traveling pawl

G67

Patent

active

040203328

ABSTRACT:
A general purpose interpolator-decimator circuit for increasing or decreasing the sampling rate of a digital signal by a factor L/M, where L and M are integers, is disclosed. The circuit includes means for determining each output sample by multiplying a sequence of previous input samples by a set of coefficients and accumulating the resulting products. L sets of coefficients, in which each coefficient is a function of the factors L and M, are stored in a specific sequence which permits sequential addressing of both the coefficients and input signal samples. A multistage decimator cascaded with a multistage interpolator to effect a narrow-band FIR filter is also disclosed.

REFERENCES:
patent: 3829670 (1974-08-01), Kebabian
patent: 3872290 (1975-03-01), Crooke et al.
Schafer et al., "A Digital Signal Processing Approach to Interpolation", Proceedings of the IEEE, June 1973, pp. 692-702.
Bellanger et al., "Interpolation, Extrapolation & Reduction of Computation Speed in Digital Filters", IEEE Trans. on Acoustics, Speech and Signal Processing, Aug. 1974, pp. 231-235.

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