Coded data generation or conversion – Analog to or from digital conversion – Digital to analog conversion
Patent
1990-03-26
1992-03-31
Pellinen, A. D.
Coded data generation or conversion
Analog to or from digital conversion
Digital to analog conversion
341153, H03M 168
Patent
active
051012049
ABSTRACT:
An interpolation DAC includes first and second registers connected to receive the X least significant and Y most significant bits of a digital input word, and are clocked to latch the X least significant bits and Y most significant bits at a first clock rate. An adder has a first group of X inputs, a second group of X inputs, X outputs, and a carry output. A third register has X inputs, and X outputs coupled to the second group of X inputs of the adder. The third register is clocked to latch the outputs of the adder at a second clock rate which is the oversampling ratio times faster than the first clock rate. A Y bit plus 1 bit DAC in which the 1 bit is a duplicate of the least significant of the Y bit section has its most significant Y bits coupled to receive the outputs of the second register. The duplicate LSB is connected to receive the carry output from the adder. A low pass filter responsive to the Y bit plus 1 bit DAC produces an analog output representative of a value of the digital input word. The digital-to-analog conversion rate of the Y bit section of the Y bit plus 1 bit DAC can be performed at the slow first clock rate.
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patent: 4963870 (1990-10-01), Obinata
Burr-Brown Corporation
Hoff Marc S.
Pellinen A. D.
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