Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
2002-09-12
2004-01-06
Lam, Tuan T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S161000, C327S233000, C327S236000
Reexamination Certificate
active
06674314
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a semiconductor integrated circuit having a DLL (delay-locked loop) for outputting a clock signal synchronized to an input clock. More particularly, the invention relates to an interpolating circuit for performing a phase adjustment, a DLL having this interpolating circuit, and a semiconductor integrated circuit, such as a DDR-SDRAM, having a DLL.
DESCRIPTION OF THE RELATED ART
BACKGROUND OF THE INVENTION
A DLL (delay-locked loop) includes a delay circuit which receives a reference clock signal as an input and which has multiple taps for outputting clock signals exhibiting different delay times, a switch for selecting two clock signals by selecting taps of the delay circuit, an interpolating circuit for outputting a signal having a phase obtained by performing interior division of the phase difference between the two clock signals, a phase detector for detecting a phase difference between the output signal of the interpolating circuit and the reference clock, and a counter for counting up or counting —down based upon an output (UP/DN) of the phase detector, whereby an output clock signal synchronized to the reference clock signal is obtained. The basic structure of such a DLL will be described with reference to
FIG. 3
used in describing the present invention.
As shown in
FIG. 3
, a delay circuit
10
is a delay circuit (termed also as delay line), to which a signal is input, for outputting a signal, which is obtained by delaying the input signal, from a tap selected from among a plurality of taps, the delay time thereof different from one another. A multiplexer
20
o
is a switch for selecting and outputting one odd-phase signal (odd) output from an odd-numbered tap of the delay circuit
10
, and a multiplexer
20
e
is a switch for selecting and outputting one even-phase signal (even) output from an even-numbered tap of the delay circuit
10
. The odd-phase signal (odd) and even-phase signal (even) that are output from the multiplexers
20
o
and
20
e,
respectively, are fed to a fine delay circuit
30
, which is composed by an interpolating circuit. A phase detector
50
detects the phase difference between the output signal of the fine delay circuit (interpolating circuit)
30
and reference clock signal to deliver its output (UP/DN) to a counter
40
. The multiplexers
20
o
and
20
e
select even- and odd-numbered taps of the delay circuit
10
based upon the output of the counter
40
. Further, on the basis of the output from counter
40
, the fine delay circuit (interpolating circuit)
30
changes the ratio of the interior division of the phase difference between the input signals.
A DLL is better suited to the low power consumption than a PLL (phase-locked loop) having a voltage-controlled oscillator because the DLL ceases operating and does not produce an output clock signal when a reference clock signal is not being applied thereto.
FIG. 12
is a diagram illustrating the structure of an interpolating circuit illustrated in the specification of Japanese Patent Kokai Publication JP-A-2001-56723. This specification discloses the interpolator circuit of a DLL used in a DDR (Double Data Rate)—SDRAM (Synchronous DRAM).
As shown in
FIG. 12
, the interpolating circuit receives internal clocks ACLK, BCLK (or /ACLK, /BCLK) and counter signals CNT
3
to CNT
0
and outputs an internal clock signal ABCLK (or /ABCLK) having a phase between the internal clocks ACLK, BCLK (or /ACLK, /BCLK). A buffer circuit adjusts the waveform of the internal clock signal ABCLK (or /ABCLK) output from the interpolating circuit and outputs an internal clock signal CLK
1
(or /CLK
1
). The interpolating circuit includes switch circuits
74
a,
74
b,
74
c,
and
74
d
that receive the internal clock signal ACLK, switch circuits
76
a,
76
b,
76
c,
and
76
d
that receive the internal clock signal BCLK, four inverters
78
and resistors R
2
and R
3
. A clocked inverter constitutes each switch and an inverter connected to a pMOS transistor of this clocked inverter. The counter signals CNT
0
to CNT
3
are supplied to control terminals of the switch circuits
74
a,
74
b,
74
c,
and
74
d,
respectively, via the inverters
78
. The numerals shown in the clocked inverters of the switch circuits represent the ratios of the gate widths of the clocked inverters, and the ON resistance of each of the clocked inverters of switches
74
a,
74
b,
74
c,
and
74
d
is one-half of that of the preceding clocked inverter. These form variable resistors in which resistance is varied in conformity with the weighting of the counter signals CNT
0
to CNT
3
. The internal clock signal ABCLK whose phase has a transition edge between the transition edge of the internal clock signal ACLK and the transition edge of the internal clock signal BCLK is formed between the resistors R
2
and R
3
. The buffer circuit includes resistors R
4
and R
5
connected serially between power supplies VDD and VSS, a differential amplifier
80
a
that receives the divided potential of resistors R
4
and R
5
, and the internal clock signal BCLK, and an inverter
80
b
that receives the output of the differential amplifier
80
a
and outputs the internal clock CLK
1
. The internal clock signal ABCLK having a phase conforming to the weighting of the counter signals CNT
0
to CNT
3
. An arrangement of the kind shown in
FIG. 14
is disclosed in the specification of Japanese Patent Kokai Publication JP-A-2001-56723 as another interpolating circuit.
As shown in
FIG. 14
, the interpolating circuit includes two sets of a constant-current source
168
a,
four P-channel MOS transistors
168
b,
168
c,
168
d,
and
168
e
of different gate widths for pulling current supplied by the constant-current source
168
a
and four N-channel MOS transistors
168
f
connected serially to the sources of respective ones of the P-channel MOS transistors, and two differential amplifier circuits
168
g,
and
168
h
whose outputs are connected to each other. The voltages at nodes v
1
and v
2
vary in accordance with the weighting of the counter signals CNT
0
to CNT
3
, thereby changing the amplifying capability of the differential amplifier circuits
168
g
and
168
h,
as a result of which the internal clock signal CLK
1
(or /CLK
1
) having a phase between the internal clocks ACLK and BCLK (or /ACLK and /BCLK) is produced as an output.
In the specification Japanese Patent Kokai Publication JP-A-2001-56723, the clock signals ACLK, /ACLK, BCLK, /BCLK supplied to the interpolating circuit shown in
FIG. 12
are selected in switch circuits by shift registers
1060
and
1064
in the manner shown in FIG.
15
.
FIG. 15
is a diagram illustrating the structure of a clock delay generator that generates the clock signals ACLK and BCLK. The clock delay generator includes a delay circuit
1054
, a delay-stage activating circuit
1056
, a first switch circuit
1058
, a first shift register
1060
, a second switch circuit
1062
and a second shift register
1064
.
In a case where a circuit for generating a tap control signal, which selects the switch that selects the tap of the delay circuit, is constituted by a shift register, the cycle necessary for locking lengthens, as will be described in detail later.
With a DDR (Double Date Rate)-II (the high-speed specification of a DDT SDRAM) having twice the operating frequency, it is necessary to raise the output timing precision. A high speed of 200 to 300 MHz (400 to 600 Mbps) is obtained with a DDR-II-SDRAM.
In a shift register for generating a tap control signal that selects the tap of the delay circuit, the step of setting a rough (coarse adjustment) initial value is at most a single stage of delay elements (delay elements
101
, etc., in FIG.
3
.).
In order to shorten lock time, it is required that the initial value of the tap (delay line) of the delay circuit be set to a median. However, locking will not necessarily be achieved in the shortest cycle. That is, the time it takes for the signal to propagate through the delay line becomes unnecessarily long and, hence,
Elpida Memory Inc.
Hayes & Soloway P.C.
Lam Tuan T.
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