Interpage prologue to protect virtual address mappings

Details Interpage prologue to protect virtual address mappings Interpage prologue to protect virtual address mappings

2005-01-18

2009-11-10

Shah, Kamini S (Department: 2128)

Data processing: structural design, modeling, simulation, and em

Emulation

Of instruction

C703S023000, C703S027000, C712S209000, C717S138000

Reexamination Certificate

active

07617088

ABSTRACT:
In a computer which translates instructions from a target instruction set to a host instruction set, a method for determining validity of a translation of a target instruction linked to an earlier translation including the steps of testing a memory address of a target instruction to be executed against a copy of the memory address of the target instruction from which a translation of the target instruction was made, executing the translation if the addresses compare, and generating an exception if the addresses do not compare.

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