Interoperable 33 MHz and 66 MHz devices on the same PCI bus

Details Interoperable 33 MHz and 66 MHz devices on the same PCI bus Interoperable 33 MHz and 66 MHz devices on the same PCI bus

1997-02-19

1998-09-15

Heckler, Thomas M.

395551, G06F 112

Patent

active

058092919

ABSTRACT:
An extended PCI bus (100) accepts both standard 33 MHz (101-102) and extended 66 MHz (103-104) PCI I/O devices, and permits the intermixing and interoperability of both types of devices on the same bus. Each extended 66 MHz initiator device (103) includes a target memory (205) that is programmed at boot up to include a list of address ranges of all extended 66 MHz devices. Each extended 66 MHz device includes a clock multiplier (202) that generates an internal 66 MHz clock signal by doubling the 33 MHz bus clock frequency. This clock multiplier may be in the form of a simple edge detecting frequency doubler (FIG. 4), or a phase locked loop (FIG. 5) that can also provide for phase adjustments to alter the skew between the bus and internal clocks. To transfer data between two extended 66 MHz devices, an extended initiator device sends, during the address/control phase of the bus cycle, a fast read or write command to the extended target device over the C/BE lines of the bus. Subsequently during the data phase of the bus cycle, data is transferred over the bus at the 66 MHz rate using the 66 MHz internal clock signals.

REFERENCES:
patent: 4344132 (1982-08-01), Dixon et al.
patent: 4688168 (1987-08-01), Gudaitis et al.
patent: 5109490 (1992-04-01), Arimilli et al.
patent: 5237676 (1993-08-01), Arimilli et al.
patent: 5263172 (1993-11-01), Olnowich
patent: 5274784 (1993-12-01), Arimilli et al.
patent: 5689660 (1997-11-01), Johnson et al.
patent: 5727171 (1998-03-01), Iachetta, Jr.
InfoWorld Jun. 3, 1996 v18 n23 p1 (2): Title: PCI bus picks up speed: Robust design will double throughput. (PCI bus technology) (Technology Information) (Brief Article) Author: Quinlan, Tom.
Microprocessor Report Jun. 17, 1996 v10 n8 p11 (5); Title: AGP speeds 3D graphics. Author: Yao, Yong.
Technical Disclosure Bulletin, vol. 38 No. 07 Jul. 1995: Title: Method of Synchronizing Data across Asynchronous Time-Division Multiplex Bus: Authors: K.B. Macauley and P.A. Manson.
A.G.P. Interface Specification Jul. 31, 1996.

Affiliated with

Also associated with

Rating

Interoperable 33 MHz and 66 MHz devices on the same PCI bus does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Interoperable 33 MHz and 66 MHz devices on the same PCI bus, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Interoperable 33 MHz and 66 MHz devices on the same PCI bus will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-100957