Multiplex communications – Wide area network – Packet switching
Patent
1996-04-12
1998-07-28
Bowler, Alyssa H.
Multiplex communications
Wide area network
Packet switching
3952006, 39520061, 39520062, 39520065, 39520075, 39520079, 3952008, 39520083, 370349, 370353, 370354, 370355, G06F 1200
Patent
active
057872554
ABSTRACT:
A special memory overlay circuit uses a first DRAM buffer memory in combination with a second faster SRAM buffer memory to reduce the time required to translate information into different network protocols. Packet data is stored in the DRAM buffer memory and packet headers requiring manipulation are stored in the SRAM buffer memory. Because the SRAM has a faster data access time than the DRAM buffer memory, a processor can reformat the packet header into different network protocols in a shorter amount of time. Packet headers also use a relatively small amount of memory compared to remaining packet data. Since the SRAM buffer memory is only used for storing packet headers, relatively little additional cost is required to utilize the faster SRAM memory while substantially increasing network performance.
REFERENCES:
patent: 5615328 (1997-03-01), Hadderman et al.
patent: 5625825 (1997-04-01), Rostoker et al.
patent: 5640399 (1997-06-01), Rostoker et al.
patent: 5651002 (1997-07-01), Van Seters et al.
patent: 5659715 (1997-08-01), Wu et al.
Kumar Shashi
Parlan Jonathan M.
Bowler Alyssa H.
Cisco Systems Inc.
Nguyen Dzung C.
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