Internet protocol layer processor

Details Internet protocol layer processor Internet protocol layer processor

1998-12-17

2002-07-09

Nguyen, Chau (Department: 2663)

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

C370S473000, C370S474000

Reexamination Certificate

active

06418145

ABSTRACT:

BACKGROUND OF THE INVENTION
(a) Field of the Invention
The present invention relates to an internet protocol (IP) layer processor for use in SAR (Segmentation And Reassemblage) of an AAL
5
frame in an ATM (asynchronous transfer mode) switching system.
(b) Description of the Related Art
In a IP packet transfer system in a conventional ATM switching system, ATM cells of an AAL
5
frame are first received in a SAR section (referred to as simply SAR hereinafter) through the ATM interface by using a virtual channel connection (VCC). The destination of IP packets is determined by a higher-level system, such as a software which runs on a CPU, to collect the AAL
5
frame for
1
P header processing, after reassembling the ATM cells into an AAL
5
frame. Thereafter, transmission is requested from the higher level system to the SAR by designating the VPI (virtual pass identifier)/VCI (virtual channel identifier) of the destinations.
FIG. 1
shows an example of conventional IP packet transfer system in an ATM switching system. A SAR
51
receives ATM cells of an AAL
5
frame through an ATM interface
56
, stores the received ATM cells in a SAR frame buffer
52
for each VCC which received the ATM cells, and at the same time, records the receipt information, such as received VPI/VCI, number of received cells and CRC calculation, in the descriptor of a SAR control memory
53
. After the receipt from the first cell to the last cell of the AAL
5
frame and reassemblage of these ATM cells into an AAL
5
frame, SAR
51
delivers a receipt notification to CPU
55
.
The AAL
5
frame, as shown in
FIG. 2
, includes a CPCS-PDU payload, a PAD and a CPCS-PDU trailer, CPCS-PDU payload including a RFC1483 header and an IP datagram. RFC
1483
header and IP datagram have a configuration such as shown in FIG.
3
.
In
FIG. 1
, after CPU
55
receives the receipt notification, CPU
55
retrieves information of the AAL
5
frame from the descriptor of SAR control memory
53
, collects the AAL
5
frame from frame buffer
52
, and makes a copy of the same in a CPU local memory
54
. The IP datagram is capsulated in the CPCS-PDU payload of the AAL
5
frame of
FIG. 2
, and it is possible to judge whether or not the capsulation of the IP datagram is completed based on a LLC/OUI/PID headers of the RFC
1483
header section added to the head of the IP datagram.
CPU
55
(and thus, software) confirms whether or not the header is correct by checking the version, the header length and the check sum of the IP header in the IP datagram. In addition, the software decrements the value of a TTL (Time To Live) field in the header, and discards the IP datagram after the value of TTL field is reduced to zero or less. The IP datagram having a normal or correct IP header and a positive value of TTL field is transferred to the next hop (or next destination). For this purpose, a destination is retrieved in a routing table formed by a layer
3
routing protocol, based on the destination address in the IP header, thereby determining the destination of the IP datagram. The IP datagram having the destination thus determined is again subjected to checking of the header check sum, so as to rewrite the IP header. Thereafter, the IP datagram is added with a RFC header, capsulated into the AAL
5
frame and transferred from SAR
51
to the specified destination after CPU
55
requests transmission from SAR
51
by designating VPI/VCI of the destination.
In the conventional IP layer processor, as described above, the software collects the AAL
5
frame received by the SAR and operates for IP header processing, followed by transmission of the same using the SAR. This causes a large time length due to the transfer of the AAL
5
frame between the SAR and the software as well as the low processing rate by the software, thereby reducing the throughput of the IP datagram transmission.
Patent Publication JP-A-9-98189 proposes an IP layer processor, wherein a controller equivalent to the SAR as described above has an additional function for processing the routing table and the IP header, whereby the IP header in the received AAL
5
frame is processed and the destination is retrieved by the controller. This enables an automated transmission (or transfer) of the AAL
5
frame without using processing by the software to thereby improve the throughput of the IP layer processor.
However, in the proposed IP layer processor, if the IP header has a defect, the automated transfer of the AAL
5
frame cannot use a function for discarding the IP datagram or generating an error message to be returned to the source address.
In some VCCs, a protocol other than the IP protocol may be used and, in addition, a plurality of protocols may be also used in a single VCC according to the RFC1483 standard, wherein the protocols in a plurality of packets capsulated in the RFC1483 header are identified. Accordingly, even in the automated transfer as proposed in the above publication, the VPI/VCI or RFC 1483 header section does not operate for IP header processing, which necessitates transfer of the protocol other than the IP protocol to the software or discard of the AAL
5
frame if the software is not provided for supporting such processing.
In addition, if a large destination retrieval table having a large number of entries is used, a large time length is required for the retrieval. Thus, in the automated transfer proposed in the publication, it may occur that a second cell or a succeeding cell of the AAL
5
frame arrives or the reassemblage of the AAL
5
frame is completed, before the destination retrieval based on the first cell of the AAL
5
frame is completed. That is, the large destination retrieval table may cause a problem in that the timing is not assured between the completion of the destination retrieval and the completion of the frame reassemblage, which complicates the timing design of the IP layer processor.
Further, as in the case of IFMP (RFC1953), layer
3
flow-switching and security function are introduced in the IP layer processing, which sometimes results in assignment of a dedicated VPI/VCI to a specified flow (such as data flow between destination address and source address or a series of packets flowing on each higher-layer protocol), in addition to assignment of a default VPI/VCI to a specific IP destination address. This necessitates the use of a plurality of retrieval tables for different retrieval conditions.
SUMMARY OF THE INVENTION
In view of the above, it is an object of the present invention to provide an IP layer processor which is capable of reducing the load of CPU.
It is another object of the present invention to provide an IP layer processor which allows a plurality of layer
3
protocols to exist on a single ATM interface.
It is another object of the present invention to provide an IP layer processor which is adapted to IFMP (IP flow management protocol) in a RFC1953 standard or RSVP (reservation protocol) in a RFC2205 standard and capable of assigning a dedicated transfer VCC to a specific flow while processing IP routing.
The present invention provides an IP layer processor comprising a cell receiving section for receiving an AAL
5
frame including a plurality of ATM cells through each virtual channel connection (VCC), a cell judgment section for judging whether or not an ATM cell received by the cell receiving section is a first cell of the AAL
5
frame, an IP header extraction section for processing the ATM cells and extracting an IP header from the ATM cell identified as the first cell by the cell judgment section, an IP header processing section for processing the IP header extracted by the IP header extraction section to generate an IP header record, a frame buffer for storing the ATM cells of the AAL
5
frame processed by the IP header extraction section and the IP header processing section, a transfer judgment section for judging whether or not the ALL
5
frame is to be transferred to a destination address based on the IP header record, a frame buffer read section for reading the ATM cells stored in the frame buffer if it is jud

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