Internally triggered electrostatic device clamp with...

Details Internally triggered electrostatic device clamp with... Internally triggered electrostatic device clamp with...

2000-08-03

2003-11-11

Toatley, Jr., Gregory J. (Department: 2836)

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

Reexamination Certificate

active

06646840

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to Electrostatic Discharge Protection (ESDP) devices. In particular, the present invention relates to triggering mechanisms for activating metal-oxide-silicon (MOS) transistors or bipolar transistors used as ESDP structures.
2. Description of the Prior Art
The fabrication of increasingly smaller integrated circuit (IC) devices has made the reliance upon effective smaller ESDP devices more important. It is well known that transient voltage surges, referred to as electrostatic discharges that may be thousands of volts, commonly occur at the terminals of IC's. These terminals are electrically coupled to active circuit components including, but not limited to, bipolar and MOS transistors. It is important to block ESD events or to divert ESD events away from the gates of transistors, particularly those transistors acting as circuit buffers, in order to ensure that the transistors are not destroyed or otherwise compromised. When that occurs, operation of the circuit can be adversely affected, including the possibility of system failure.
As ESD problems are widespread, wide arrays of solutions have been developed. For the most part, these solutions have involved the placement of low-breakdown transistors or diodes in parallel with the circuit to be protected. The transistor or diode is designed to be non-conducting under expected potential values, and conducting when a potential on an input or output buffer node exceeds those expected values. When turned on by the higher-than-expected potential, the ESD device is designed to divert inordinately high current associated with such transient conditions away from the circuit to which the ESD device is connected. Commonly, it is desirable to have the transient current diverted to a low-potential power rail, generally defined as ground. N-type MOS (NMOS) ESDP transistors are often used to achieve that end.
More recently, pluralities of NMOS transistors have been employed in parallel combination to provide protection. However, it is important in such a configuration to make sure that each of the individual transistors making up the composite transistor turns on at substantially the same time. Failure to do so will result in the first of the transistors in the set to turn on to support the entire transient load. That generally causes failure of that transistor unit as well as the entire ESD protection device. Ballast resistance is required in these devices as a means to alleviate problems of non-simultaneous turn-on; however, the ballast that is often required can lead to unacceptable increases in transistor set size. Variations occurring during processing of the prior ballasted ESD devices further tend to yield unreliable ESD protection, particularly where vertical pathways and field oxides were relied upon to provide the resistance. It is well known that such pathways can vary substantially in resistance from one site to another.
One particular ESDP device includes a MOS transistor having its gate coupled to a triggering mechanism. Like the MOS transistor, the trigger is coupled in parallel to the circuit to be protected. The transistor and trigger are designed to operate as follows. The transistor is configured to conduct relatively high currents of the type that may be expected under typical electrostatic conditions, such as those currents associated with human body model spikes. The transistor is also configured to clamp across itself a potential that keeps the circuit to be protected unharmed. A generic representation of the trigger-based ESDP device is shown in FIG.
1
. The protected circuit
10
exists between supply pads
20
and
30
. An ESD transistor M
1
that is typically an N-type MOS transistor, is coupled in parallel with the circuit
10
. Finally, a trigger
40
coupled in parallel with the circuit
10
has an output coupled to the gate of M
1
.
In intended operation, the trigger
40
activates at a desired standoff voltage. The transistor action of transistor M
1
thereby clamps the potential applied to circuit
10
, preferably at a level and in time to ensure that circuit
10
will not be damaged by the overvoltage event. Ideally, the trigger
40
does not interfere with the standard operation of the circuit
10
when there is no discharge event. It should not turn on too slowly in relation to the discharge event and it should not interfere with the operation of the primary ESD transistor M
1
. Preferably, the trigger
40
consumes little space on a die and does not cause premature degradation of the entire circuit structure.
Common prior ESDP devices are shown in
FIGS. 2 and 3
, each of which includes the NMOS primary ESD transistor M
1
coupled in parallel with the circuit
10
to be protected. The device of
FIG. 2
includes as the trigger an RC gate pump branch formed of a capacitor C
1
in series with a resistor R
1
. The high-potential node of resistor R
1
is connected to the gate of M
1
. The RC branch activates the ESDP transistor M
1
by pumping up the potential of its gate to a value beyond the threshold potential. The RC branch effectively lowers the trigger potential of that transistor, and can do so uniformly for a plurality of ESDP transistor elements. That is, transistor M
1
turns on before the potential at either of the pads
20
and
30
exceeds a value dangerous for the circuit
10
. The transistor M
1
thereby diverts current from one pad to the other before damage occurs.
That is the ideal operation of the ESDP device of FIG.
2
. However, there are disadvantages associated with the RC branch trigger design. First, as circuits become increasingly smaller and preferably increasingly faster, it is generally undesirable to insert capacitance of the magnitude required for a suitable ESDP device. Second, the additional capacitance may create a pad-to-pad leakage pathway resulting in performance loss, particularly under rapid signal transition conditions. Finally, dependent upon the characteristics of the discharge event, the RC branch may turn on and then turn off before all discharge elements of transistor M
1
are fully engaged, while the discharge event remains detrimental to the circuit
10
. Alternatively, the pulse may not be long enough to pump up the capacitor C
1
enough to reach the threshold gate potential of transistor M
1
so as to turn on that transistor and thereby protect the circuit
10
.
The second relatively common ESDP device of the prior art is shown in FIG.
3
. In that device, the trigger is a Zener diode Z
1
that essentially replaces the capacitor C
1
of FIG.
2
. However, the Zener diode Z
1
is preferable when the delay associated with the capacitor charging is undesirable in regard to operation of the circuit
10
to be protected. The Zener diode Z
1
is fabricated so as to breakdown at a voltage less than that determined to be suitable for the circuit
10
. However, the protection circuit of
FIG. 3
may be deficient under certain conditions. Specifically, if the circuit
10
requires a relatively low breakdown potential in order to be protected, and the process-available breakdown voltage and range of the Zener diode Z
1
may simply be too high. That may be of particular concern when mixed power supplies (e.g., 5-volt nominal and 3.3-volt nominal supplies are used for coupled circuitry) are involved and multiple voltage protection levels are required. Under certain conditions, the transistor M
1
may be turned off if the base drive to the effective internal parasitic lateral bipolar transistor of M
1
is insufficient for bipolar action without pumping up the gate potential. Below the Zener diode Z
1
breakdown voltage, current produced by Zener breakdown in diode Z
1
through R
1
falls and the potential at the gate of Ml drops too low to keep it on. Nevertheless, the discharge event may remain and could damage circuit
10
. A trigger that fails to remain on when the ESD protection transistor M
1
is on, reduces the efficiency of the protective structure and could result in premature lo

Affiliated with

Also associated with

Rating

Internally triggered electrostatic device clamp with... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Internally triggered electrostatic device clamp with..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Internally triggered electrostatic device clamp with... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3169146