Internal voltage step-down circuit

Details Internal voltage step-down circuit Internal voltage step-down circuit

2002-10-29

2004-07-27

Berhane, Adolf (Department: 2838)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

With specific source of supply or bias voltage

Reexamination Certificate

active

06768370

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to an internal voltage step-down circuit and more particularly to an internal voltage step-down that may reduce an externally applied power source voltage to a predetermined internal voltage that may be provided to an internal circuit such as a semiconductor integrated circuit.
BACKGROUND OF THE INVENTION
In order to increase the capacity of a semiconductor storage device and/or decrease manufacturing costs, device elements (such as transistors) are made smaller or further miniaturized. However, as transistors, such as metal oxide semiconductor field effect transistors (MOSFETs), are made smaller, gate oxide films are reduced. Thus, the breakdown voltage of the gate oxide films are reduced and a power source voltage supplied to the semiconductor integrated circuit must be reduced. Therefore, an internal power source voltage step-down system is conventionally used to reduce an externally applied power source voltage to a predetermined internal source voltage. The internal source voltage is then supplied to internal circuits such as a semiconductor integrated circuit. Additionally, in order to reduce power consumption in a system, the externally applied power source can be reduced.
Referring now to
FIG. 15
, a circuit schematic diagram of a conventional internal voltage step-down circuit and an internal circuit is set forth.
In
FIG. 15
, a conventional internal voltage step-down circuit
10
receives an external power source voltage V
DD
and a reference voltage V
REF
and provides an internal voltage V
INT
to an internal circuit
1
through an internal power source line
13
. Conventional internal voltage step-down circuit
10
includes a differential amplifier
11
and a driver p-channel MOSFET (hereinafter referred to as a PMOS transistor)
12
. Differential amplifier
11
receives reference voltage V
REF
at an inverting input terminal (indicated with a minus−) and internal voltage V
INT
at a non-inverting input terminal (indicated with a plus +) and provides an output to a gate electrode of driver PMOS transistor
12
. Driver PMOS transistor
12
has a source electrode connected to receive external power source voltage V
DD
and a drain connected to internal power source line
13
. In this way, conventional internal voltage step-down circuit
10
provides internal voltage V
INT
at the drain of driver PMOS transistor
12
. Internal voltage V
INT
is a stepped-down voltage from external power source voltage V
DD
.
One or plural internal circuits
1
which consume an operating current I are connected to the internal power source line
13
to receive internal voltage V
INT
as a power source. In this way, internal voltage V
INT
is obtained by dividing external power source V
DD
by an impedance between the source and the drain of driver PMOS transistor
12
and an internal impedance of internal circuit
1
.
In conventional voltage step-down circuit
10
, differential amplifier
11
compares internal voltage V
INT
on internal power source line
13
with reference voltage V
REF
. For example, when internal voltage V
INT
becomes lower than reference voltage V
REF
, an output voltage of differential amplifier
11
is reduced. Thus, driver PMOS transistor
12
becomes more conductive to increase a current from external power source voltage V
DD
. As a result, internal voltage V
INT
rises. On the other hand, when internal voltage V
INT
becomes higher than reference voltage V
REF
, an output voltage of differential amplifier
11
is increased. Thus, driver PMOS transistor
12
becomes less conductive to reduce a current from external power source voltage V
DD
. As a result, internal voltage V
INT
drops. Through this feedback operation, internal voltage V
INT
is controlled to be equal to reference voltage V
REF
.
When memory access is not conducted, internal circuit
1
can be in an inactive state (standby mode). In this case, internal current I is a minute current on the order of a device leakage current of devices in internal circuit
1
. Thus, a current I
0
output through driver transistor
12
is also a minute current on the order of the device leakage current of devices in internal circuit
1
and internal voltage V
INT
is controlled such that it is equal to reference voltage V
REF
. On the other hand, when an active signal (such as an active signal pulse) is input to internal circuit
1
and internal circuit
1
is active, and the switching of devices in internal circuit
1
causes a higher internal current I. With a higher internal current I, the internal voltage V
INT
can be reduced. However, through the feedback operation of conventional step-down circuit
10
, the control gate terminal of driver PMOS transistor
12
is pulled lower and the impedance of driver PMOS transistor
12
lowers. In this way, current I
0
flowing external power source voltage V
DD
to internal voltage V
INT
increases and internal voltage V
INT
is controlled to be equal to reference voltage V
REF
.
However, when the potential of external power source voltage V
DD
is reduced, for example to reduce overall system power consumption, a potential difference between external power source voltage V
DD
and internal voltage V
INT
becomes small. Thus, the potential difference across driver PMOS transistor
12
is decreased and it becomes difficult to provide sufficient current I
0
to maintain internal voltage V
INT
to the same potential as to reference voltage V
REF
. For example, when internal voltage V
INT
is 1.5 V and external power source voltage V
DD
is 1.8 V or less, a potential different between external power source voltage V
DD
and internal voltage V
INT
is 0.3 V or less, thus the potential difference between the source and the drain of driver PMOS transistor
12
is 0.3 V or less. With such a small potential difference between the source and the drain, driver PMOS transistor
12
may not provide sufficient current I
0
to maintain internal voltage V
INT
to the same potential as to reference voltage V
REF
.
In particular, when an active signal is input and internal circuit
1
is in an active state, internal current I can rapidly increase. In this case, conventional voltage step-down circuit
1
has a delayed response before a reduced internal voltage V
INT
is restored to the potential of internal reference voltage V
REF
. Alternatively, when internal circuit
1
is switched from an active (operating) state to a standby (non-operating) state, internal current I is reduced to the leakage current of devices in internal circuit
1
, voltage conventional voltage step-down circuit
1
cannot respond quickly to reduce output current I
0
and overshoot occurs in the potential of internal voltage V
INT
. Operation of internal circuit
1
can be affected by such a variation in an internal power source voltage such as internal voltage V
INT
.
In order to improve the current capability of driver PMOS transistor
12
in conventional voltage step-down circuit
10
, channel width W can be increased. When channel width W of driver PMOS transistor
12
increases, an operating current of differential amplifier
11
can be increased to increase amplification sensitivity and/or drive current. In this way, a response speed of conventional voltage step-down circuit
10
is increased to suppress variations in internal voltage V
INT
providing an internal power source. However, such an approach increases power consumption and/or the chip area occupied by conventional voltage step-down circuit
10
.
In a dynamic random access memory (DRAM), a large current amount is consumed over a short period of time during a sense operation. When a conventional internal power source voltage step-down circuit is used to convert an external power source voltage into a predetermined internal voltage to provide a power supply for sensing operations or the like in a DRAM, a technique has been employed in which a driver PMOS transistor is automatically turned on in response to a trigger signal in anticipation of the large current demand. For example, i

Affiliated with

Also associated with

Rating

Internal voltage step-down circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Internal voltage step-down circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Internal voltage step-down circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3204689