Internal voltage generator using anti-fuse

Details Internal voltage generator using anti-fuse Internal voltage generator using anti-fuse

1999-06-29

2001-11-27

Cunningham, Terry D. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

Fusible link or intentional destruct circuit

C327S541000

Reexamination Certificate

active

06323720

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an internal voltage generator for a semiconductor device, and more particularly to an internal voltage generator using anti-fuse which is capable of conveniently trimming the internal voltage to be suitable for an external environment even at the packaging step for fabricating the semiconductor device.
2. Description of the Prior Art
An internal voltage generator is widely used in order to drive a semiconductor device in a chip with a relatively low voltage. The internal voltage generator receives an external voltage of a high level so as to generate new internal voltages in the chip. Using the internal voltages, the chip can reduce power consumption therein, and operate more rapidly.
The internal voltage should have a predetermined lever regardless of variations in the external voltage, a temperature around the chip, and a process.
FIG. 1
is a block diagram showing a conventional internal voltage generator.
As shown in this drawing, the conventional internal voltage generator comprises a first voltage generator
1
for producing a voltage Vr
1
which has a constant level irrespective of variations in the temperature or the external voltage, a decoding unit
2
for generating signals s
0
to s
7
according to a selective blowing of fuses therein, and a second voltage generator
3
for amplifying the voltage Vr
1
from the first voltage generator
1
in response to the signals s
0
to s
7
from the decoding unit
2
, thereby generating a amplified voltage Vr
2
.
The conventional internal voltage generator further comprises a third voltage generator
4
for making an internal voltage Vr according to the output voltage Vr
2
of the second voltage generator
3
, and a fourth voltage generator
5
for producing an activation voltage Vact in the case that the DRAM becomes active.
The conventional internal voltage generator further comprises a first voltage drive unit
6
for controlling an internal voltage Vint in a standby state of the DRAM according to the voltages Vr
1
and V
1
, which are applied by the first and the third voltage generators
1
and
4
, respectively.
In addition, the conventional internal voltage generator comprises a second voltage drive unit
7
for controlling the internal voltage Vint when the DRAM operates on the basis of the voltages Vr
1
, Vr and Vact, which are applied by the first, third and fourth voltage generators
1
,
4
and
5
, respectively.
Typically, the first voltage generator
1
is provided with a Widlar reference voltage generator.
As shown in
FIG. 2
, the decoding unit
2
includes fuse units F
1
, F
2
and F
3
for receiving an external voltage Vext through their input terminals to respectively generate signals rep
1
and repb
1
, rep
2
and repb
2
, and rep
3
and repb
3
. The decoding unit
2
further includes an output unit DOUT
1
for logically combining the signals rep
1
to rep
3
and, repb
1
to repb
3
in order to make the signals s
0
to s
7
prior to supplying the second voltage generator
3
with the signals s
0
to s
7
.
The output unit DOUT
1
includes NAND gates NAND
1
to NAND
8
for being enabled by the external voltage Vext and outputting the signals of a low level in the case that all of three signals among the signals rep
1
to rep
3
and repb
1
to rep
3
have a high level. The output unit DOUT
1
further includes inverters IN
1
to IN
8
for being enabled thereby, and inverting the signals from the NAND gates NAND
1
to NAND
8
prior to supplying the second voltage generator
3
with the signals s
0
to s
7
.
As shown in
FIG. 3
, the fuse unit F
1
in the decoding unit
2
includes a charging unit
8
for being charged by the external voltage Vext applied via a fuse PF, and an output unit Fout for buffering the voltage charged in the charging unit
8
after being enabled thereby and then applying the signals rep
1
and repb
1
to the output unit DOUT
1
. The fuse unit F
1
further comprises a discharging unit
9
for being driven by the signal from the output unit FOUT, thereby completely discharging the voltage of the charging unit
8
when the fuse PF is blown.
The charging unit
8
and the discharging unit
9
are made of a decoupling capacitor N
8
and a N-channel MOS transistor N
9
, respectively.
The output unit FOUT includes inverters IN
9
, IN
10
and IN
11
for being enabled thereby and sequentially coupled to the charging unit
8
, the discharging unit
9
and the fuse PF in common, wherein the output terminal of the inverter IN
9
is also coupled to the gate of the N-channel MOS transistor N
9
included in the discharging unit
9
, and the inverters IN
10
and IN
11
generate the signals repb
1
and rep
1
, respectively.
The fuse units F
2
and F
3
included in the decoding unit
2
are the same as the above mentioned fuse unit F
1
in their constructions.
Hereinafter, the operation of the conventional internal voltage generator will be described in detail referring to the attached drawings.
As shown in
FIG. 1
, the second voltage generator
2
amplifies the voltage Vr
1
, which is applied by the first voltage generator
1
on the basis of the signals s
0
to s
7
from the decoding unit
2
. In this case, the decoding unit
2
logically combines the signals rep
1
to rep
3
and repb
1
to repb
3
and then generates the signals s
0
to s
7
, as shown in FIG.
2
.
Namely, with reference to
FIG. 3
, the output signal of the inverter IN
9
is applied to the gate of the N-channel MOS transistor N
9
included in the charging unit
9
. Therefore, the N-channel MOS transistor N
9
is turned on in response to the high level signal from the inverter IN
9
when the fuse PF is blown, thereby causing the voltage charged in the decoupling capacitor N
8
to be discharged rapidly. At this time, the signal rep
1
is pulled up to the high level, whereas the signal repb
1
is pulled down to the low level.
In this manner, if at least one of the fuses is selectively blown in accordance with the operation state of the DRAM, the decoding unit
2
supplies the second voltage generator
3
with the signals s
0
to s
7
after logically combining the signals rep
1
to rep
3
and repb
1
to repb
3
. The second voltage generator
3
amplifies the input voltage Vr
1
to be the voltage Vr
2
having a desired level, such that the internal voltage Vint is consequently generated.
The fuses included in the fuse units F
1
, F
2
and F
3
are made of poly-silicon and can be blown by a laser beam.
In the case of cutting polysilicon using a laser beam, this laser cutting method suffers from disadvantages such that an error may occur in accurately applying the laser beam to the polysilicon and a residue may remain around the disconnection part after the cutting. Another disadvantage of the laser cutting method is in that a large amount of processing time is required, and it is difficult and inaccurate to perform the method. Further, the laser cutting method has another disadvantage such that it is impossible to trim the level of the internal voltage at a packaging process of the semiconductor device, resulting in a degradation in reliability of the semiconductor device.
SUMMARY OF THE INVENTION
Therefore, it is an object of the present invention to provide an internal voltage generator using anti-fuse for being capable of conveniently trimming the internal voltage to be suitable for an external environment even at a packaging step of fabricating the semiconductor device.
It is another object of the present invention to provide an internal voltage generator using anti-fuse for rapidly blocking a current path established through the anti-fuse after the anti-fuse is programmed, thereby reducing a current amount consumed when the anti-fuse is programmed.
To accomplish the above mentioned object, the present invention provides an internal voltage generator using anti-fuses which trims an inputted voltage on the basis of decoding signals from a decoding unit and then generates internal voltages having a level different from each other, comprising: buffer mean

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