Internal voltage generation circuit

Details Internal voltage generation circuit Internal voltage generation circuit

2001-01-17

2002-10-29

Zweizig, Jeffrey (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

With specific source of supply or bias voltage

Reexamination Certificate

active

06472926

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to internal voltage generation circuits and particularly to a configuration of a circuit for generating a boosted voltage used in a dynamic random access memory.
2. Description of the Background Art
A dynamic random access memory (DRAM), widely used as main memory, is formed mainly through a CMOS (complementary metal-insulating film-semiconductor) process. The DRAM has a memory cell configured of a capacitor and a single access transistor. This access transistor is generally formed of an n-channel MOS transistor having a larger charge driving capability than a p-channel MOS transistor (an insulated gate field effect transistor).
To store data of a high level in this memory cell capacitor, a boosted voltage Vpp higher than a normal voltage corresponding to high level data is applied to a gate of the access transistor, with its threshold voltage loss considered. Typically, the DRAM is internally provided with a booster circuit (a Vpp generation circuit) for obtaining boosted voltage Vpp from an external power supply voltage ExVdd supplied from an outside of the chip (DRAM). Incorporating the Vpp generation circuit reduces current consumption due to dispensable charging and discharging a line transmitting the boosted voltage, and simplifies a system power supply arrangement, as compared to a configuration of externally generating boosted voltage Vpp and supplying boosted voltage Vpp to a DRAM.
FIG. 24
shows an example of a configuration of a conventional Vpp generation circuit. In
FIG. 24
, the Vpp generation circuit includes a rectifying element (a diode) D
1
connected between an external power supply node ND
1
and a node ND
2
, a rectifying element D
2
connected between node ND
2
and an output node ND
3
, and a capacitance element C
1
supplying electric charge to node ND
2
in response to a pump clock signal &phgr;. Rectifying element D
1
has an anode connected to external power supply node ND
1
and a cathode connected to node ND
2
. Rectifying element D
2
has an anode connected to node ND
2
and a cathode connected to node ND
3
. Pump clock signal &phgr; has a predetermined period and a predetermined amplitude.
When pump clock signal &phgr; is at a low level, rectifying element D
1
conducts and node ND
2
is precharged to a voltage level of ExVdd−Vth. Herein, Vth represents a forward voltage drop of rectifying elements D
1
and D
2
. When pump clock signal &phgr; rises to a high level, node ND
2
has its voltage level increased by an amplitude Vcc of pump clock signal &phgr;. More specifically, the voltage level of node ND
2
increases to a voltage level of Vcc +ExVdd−Vth. Rectifying element D
2
conducts as the voltage level of node ND
2
increases, and rectifying element D
2
supplies electric charge to node ND
3
and increases boosted voltage Vpp in voltage level. By repeating this operation, boosted voltage Vpp rises to at most a voltage level of ExVdd+Vcc−2·Vth. If pump clock signal &phgr; has an amplitude equal to external power supply voltage ExVdd, boosted voltage Vpp accordingly rises to a voltage level of 2·ExVdd−2·Vth.
In the Vpp generation circuit as shown in
FIG. 24
, capacitance element C
1
has an charge supplying capability substantially proportional to the capacitance value of capacitance element C
1
, since Q=C·V.
FIG. 25
schematically shows a configuration of a portion generating boosted voltage Vpp in a conventional DRAM. In
FIG. 25
, an active Vpp generation circuit
902
and a standby Vpp generation circuit
904
are provided for a DRAM circuit
906
. Active Vpp generation circuit
902
is activated in an active cycle of DRAM circuit
906
(when a memory cell select operation is performed) to generate boosted voltage Vpp. Standby Vpp generation circuit
904
normally operates and compensates for a reduction of boosted voltage Vpp caused by a leak current when DRAM circuit
906
is in a standby state. Therefore, standby Vpp generation circuit
904
is adapted to have a small current driving capability and active Vpp generation circuit
902
is adapted to have a large current driving capability. For example, boosted voltage Vpp is used not only for a word line drive signal but also for bit line isolation instructing signal in a shared sense amplifier configuration. Boosted voltage Vpp is also used for a bit line equalization instructing signal for equalizing bit lines, to rapidly precharge/equalize the bit lines.
In the active cycle, the bit line isolation and equalization instructing signals are charged and discharged (the signals are discharged when the active cycle starts and the signals are charged when the active cycle is completed) and further boosted voltage Vpp is consumed in selecting a word line. Therefore, in the active cycle, active Vpp generation circuit
902
having a large current driving capability is activated and generates boosted voltage Vpp with the large current driving capability reliably.
Typically, a DRAM has a plurality of modes of operation, and, as has been described previously, a Vpp generation circuit is required to have different current supplying capabilities for different modes of operation and the DRAM has a specification value of power consumption that varies in correspondence to the mode of operation. In a standby cycle, minimizing power consumption is required. Therefore, active Vpp generation circuit
902
having a large current supplying capability and a large power consumption and standby Vpp generation circuit
904
having a small current supplying capability and a small power consumption are used to supply DRAM circuit
906
with boosted voltage Vpp. Active Vpp generation circuit
902
and standby Vpp generation circuit
904
are selectively activated depending on a mode of operation of the DRAM circuit to satisfy a current supplying capability of a Vpp generation circuit and a specification value for power consumption of the DRAM.
Active Vpp generation circuit
902
and standby Vpp generation circuit
904
both utilize the charge pump circuit as shown in FIG.
24
. If boosted voltage Vpp is generated by a charge pump circuit and boosted voltage Vpp has a voltage level dropping due to leak current or consumption thereof, boosted voltage Vpp varies in a saw-tooth form. More specifically, as shown in
FIG. 26
, when pump clock signal &phgr; goes high, node ND
2
has a voltage level increased from a precharge voltage level by an amplitude of pump clock signal &phgr;. In response to the increase of the voltage level, rectifying element D
2
conducts and supplies electric charge to node ND
3
. In response to the supply of electric charge, boosted voltage Vpp has a voltage level increasing rapidly.
If boosted voltage Vpp drops in level because of consumption of boosted voltage Vpp through an operation of an internal circuit or because of a leak current through a leak path, node ND
2
has a voltage level gradually lowered since electric charge is applied from node ND
2
to node ND
3
when pump clock signal &phgr; is held high. When pump clock signal &phgr; falls low, node ND
2
has a voltage level once dropped and again rectifying element D
1
allows node ND
2
to return to the precharge voltage level. When pump clock signal &phgr; is held low, rectifying element D
2
does not conduct and boosted voltage Vpp continues to lower. This operation is repeated and boosted voltage Vpp has a saw-tooth like voltage waveform. In particular, in active Vpp generation circuit
902
, capacitance element C
1
has a capacitance value sufficiently increased to accommodate a large current consumption in the active cycle, and a large amount of electric charge is transferred to node ND
2
and electric charge is rapidly supplied from node ND
2
via rectifying element D
2
to node ND
3
. Thus, the saw-tooth waveform becomes large in amplitude.
A circuit configuration employing a multi-phase clock signal to provide a charge pump operation, as shown in
FIG. 27
, to minimize the variation of boosted voltage Vp

Affiliated with

Also associated with

Rating

Internal voltage generation circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Internal voltage generation circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Internal voltage generation circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2999418