Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
2003-01-09
2004-08-03
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
C327S541000, C327S407000
Reexamination Certificate
active
06771115
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an internal voltage generating circuit and, in particular, to an internal voltage generating circuit to reduce current consumption in a standby state of a semiconductor memory device.
2. Description of the Background Art
FIG. 8
is a functional block diagram illustrating functions of an exemplary conventional internal voltage generating circuit for a semiconductor memory device.
Referring to
FIG. 8
, the internal voltage generating circuit includes a boosting pump
1
, a reference voltage generating circuit
2
, a level sensing circuit
3
, a voltage dividing circuit
4
for dividing a boosted voltage VPP, a resistor
5
connected to an output node of boosting pump
1
, and a capacitor
6
connected between resistor
5
and the ground potential.
In this configuration, boosting pump
1
supplies a maximum output voltage EXT2 which can be driven by a charge pump operation, and accordingly boosted voltage VPP is generated through capacitive coupling of capacitor
6
.
Boosted voltage VPP is then divided by voltage dividing circuit
4
and a resultant voltage, namely divided voltage VDIVH is supplied to one input of level sensing circuit
3
. Reference voltage generating circuit
2
generates a reference voltage VREFH having a voltage level corresponding to a target level of an internal voltage, and this reference voltage is supplied to the other input of level sensing circuit
3
.
Level sensing circuit
3
receives two signals respectively of divided voltage VDIVH and reference voltage VREFH to compare the level of voltage VDIVH with the level of voltage VREFH. If the level of voltage VDIVH is lower than that of voltage VREFH, level sensing circuit
3
outputs a sense signal (PMPE signal) of H (logical high) level to boosting pump
1
. If the level of voltage VDIVH is higher than the level of voltage VREFH, level sensing circuit
3
outputs PMPE signal of L (logical low) level to boosting pump
1
.
Boosting pump
1
performs a charge pump operation in a period in which PMPE signal has H level to generate the maximum output voltage EXT2 which can be driven, and boosted voltage VPP is accordingly generated through capacitive coupling of capacitor
6
. If PMPE signal has L level, no charge pump operation is conducted by boosting pump
1
.
FIG. 9
is a detailed circuit diagram of an exemplary reference voltage generating circuit
2
as shown in FIG.
8
.
Referring to
FIG. 9
, reference voltage generating circuit
2
includes p-channel transistors
7
and
8
, n-channel transistors
9
and
10
connected in series to p-channel transistors
7
and
8
, a p-channel transistor
11
constituting a current mirror circuit together with p-channel transistor
8
, and a resistor
12
.
P-channel transistors
7
and
8
have respective sources connected to a power supply node of an external power supply Vdd
13
and respective drains connected to respective drains of n-channel transistors
9
and
10
. The drain of p-channel transistor
8
is also connected to respective gates of p-channel transistors
7
,
8
and
11
and the drain of p-channel transistor
7
is also connected to respective gates of n-channel transistors
9
and
10
. Respective sources of n-channel transistors
9
and
10
are grounded. The source of p-channel transistor
11
is connected to the power supply node of external power supply Vdd
13
and the drain thereof is grounded via resistor
12
. The point of connection of the drain of p-channel transistor
11
and resistor
12
composes an output terminal of reference voltage VREFH.
In the configuration shown in
FIG. 9
, p-channel transistors
7
and
8
constitute a current mirror circuit, and a mirror current of the current flowing through p-channel transistor
8
flows through p-channel transistor
7
.
Similarly, p-channel transistors
9
and
10
constitute a current mirror circuit, and a mirror current of the current flowing through p-channel transistor
9
flows through n-channel transistor
10
.
As the drive current of p-channel transistor
8
is equal to the drive current of n-channel transistor
10
, the current flowing through each of the transistors is uniquely determined by the drive current of n-channel transistor
9
and thus is dependent on an external power supply voltage to a small degree.
In addition, a mirror current of the current flowing through p-channel transistor
8
flows through p-channel transistor
11
and resistor
12
, and predetermined reference voltage VREFH corresponding to the target level of boosted voltage VPP is output.
FIG. 10
is a detailed circuit diagram showing an exemplary voltage dividing circuit
4
.
Voltage dividing circuit
4
is composed of diode-connected p-channel transistors
14
and
15
provided in series between boosted voltage VPP and the ground potential, and divided voltage VDIVH of boosted voltage VPP is output from the drain of p-channel transistor
15
.
FIG. 11
is a circuit diagram showing a configuration of an exemplary level sensing circuit
3
.
Level sensing circuit
3
includes a comparator detecting a potential difference between divided voltage VDIVH of boosted voltage VPP and reference voltage VREFH, and an inverter
21
inverting the result of the comparison to output sense signal PMPE.
The comparator includes a current-mirror differential amplifier composed of p-channel transistors
16
and
17
having respective sources connected to external power supply Vdd
13
and serving as load, an n-channel transistor
18
having its gate receiving divided voltage VDIVH and an n-channel transistor
19
having its gate receiving reference voltage VREFH, and an n-channel transistor
20
provided between the current-mirror differential amplifier and the ground potential and having its gate receiving a control voltage VCNTN which is set approximately at a threshold for the purpose of reducing the current flowing through the current-mirror differential amplifier.
In the configuration shown in
FIG. 11
, respective voltage levels of reference voltage VREFH and divided voltage VDIVH are compared with each other. If the level of voltage VREFH is higher than the level of voltage VDIVH, n-channel transistor
19
is turned on to pass a larger electric current so that the potential on the drain of p-channel transistor
17
has L level which is inverted by inverter
21
and accordingly PMPE signal of H level is output.
If the level of voltage VDIVH is higher than the level of voltage VREFH, n-channel transistor
18
is turned on to pass a larger electric current so that the potential on the drain of p-channel transistor
17
has H level and accordingly PMPE signal of L level is output from inverter
21
.
FIG. 12
is a detailed circuit diagram showing an exemplary boosting pump
1
as shown in FIG.
8
.
Referring to
FIG. 12
, boosting pump
1
is composed of a pump drive signal generating circuit
22
and a pump circuit
23
.
Pump drive signal generating circuit
22
includes a two-input NAND circuit
28
having a first input node receiving, via inverters
24
and
25
, a clock signal of a certain fixed cycle generated by a delay circuit constituted of an odd number of delay stages (odd-number-stage delay circuit)
27
, and a second input node receiving PMPE signal from level sensing circuit
3
, and an inverter
26
connected to an output node of two-input NAND circuit
28
. Inverter
26
has its output node connected to respective input nodes of inverters
29
and
31
in pump circuit
23
.
In this configuration, if PMPE signal has H level, the clock signal of the fixed cycle generated by odd-number-stage delay circuit
27
is output as a pump drive signal (PCLK signal) to respective input nodes of inverters
29
and
31
in pump circuit
23
.
Pump circuit
23
includes inverters
29
,
30
,
31
,
32
,
33
and
34
, capacitors
35
and
36
, and n-channel transistors
37
,
38
and
39
.
Inverters
29
and
31
have respective input nodes receiving PCLK signal supplied from pump drive signal generating circuit
22
.
Inverter
30
conne
Cunningham Terry D.
McDermott Will & Emery LLP
Renesas Technology Corp.
Tra Quan
LandOfFree
Internal voltage generating circuit with variable reference... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Internal voltage generating circuit with variable reference..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Internal voltage generating circuit with variable reference... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3344114