Internal voltage generating circuit

Details Internal voltage generating circuit Internal voltage generating circuit

2001-01-16

2002-07-30

Cunningham, Terry D. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

With specific source of supply or bias voltage

C327S512000

Reexamination Certificate

active

06426671

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an internal voltage generating circuit for generating an internal voltage of a level between the levels of an external supply voltage and a ground voltage. Specifically, the present invention relates to an internal voltage generating circuit for generating a temperature-independent internal voltage. More specifically, the invention relates to a configuration of a circuit for generating an internal voltage determining a voltage level of data stored in a memory cell in a semiconductor memory device.
2. Description of the Background Art
With recent developments of computers and information processing terminals, requirements are becoming severer for memories employed as main memories in these devices and equipment. Specifically, in addition to a large storage capacity, speed-up of an effective data transfer rate as well as reduction of power consumption are strongly required for application to portable equipment. To consider, as an example, DRAMs (Dynamic Random Access Memories) used most widely as main memory devices, DRAMs capable of transferring data at a high clock rate, such as an SDRAM (Synchronous DRAM) inputting/outputting data synchronously with a clock signal and a DDR (Double Data Rate) SDRAM inputting/outputting data synchronously with both of the rising and falling edges of a clock signal, are coming into wide use.
In a DRAM, information is stored in the form of charges in a capacitor of a memory cell. If data of H (high) level written in a DRAM cell is left as it is, the data would be lost in the course of time due to a leakage current. Therefore, a periodic restoring operation called refresh is required in DRAMs.
For recent DRAMs, an operation referred to as self refresh is defined by specifications. In this self refresh operation mode, an internal timer provided in a DRAM automatically sets a refresh timing, and the refresh operation is automatically carried out according to this refresh timing. The self refresh operation is performed in a standby period in which no access is made to the DRAM. Accordingly, reduction of a self refresh current consumed in the refresh operation can decrease current consumption of the DRAM and thus extend the life of a battery in a battery-driven information communication terminal of a portable type, for example, thereby to lengthen a continuous standing-by time.
In order to reduce the self refresh current, data holding characteristics of a memory cell should be improved to extend an interval Tsrc between refresh operations. In terms of manufacturing process, the improvement is accomplished by: (1) using a material of a high dielectric constant as an insulating film for a memory cell capacitor or devising a shape of the memory cell capacitor for increasing the capacitance value of the memory cell capacitor, and (2) reducing an off-leakage (subthreshold leakage) current Ilb of a memory cell transistor and a leakage current Ils in a PN junction between a memory cell capacitor electrode and a semiconductor substrate.
In terms of circuit design, the data holding characteristics of the memory cell can be improved by devising a power supply arrangement in a memory cell array. As one of approaches for improvement in terms of the circuit design, a BSG (Boosted Sense ground) scheme is proposed by Asakura et al. Details of the BSG scheme are described, for example, in IEEE Journal of Solid-State Circuits, 1994, pp. 1303-1309. A brief description is given below of principles of the BSG scheme.
FIG. 16
schematically shows a cross sectional structure of a memory cell of a conventional DRAM. In
FIG. 16
, the memory cell includes high-concentration N type impurity regions
502
a
and
502
b
formed at a surface of a semiconductor substrate
500
with an interval therebetween, a conductive layer
504
formed on the channel region between impurity regions
502
a
and
502
b
with a gate insulating film
503
underlaid, and a conductive layer
505
connected electrically to impurity region
502
a.
On these conductive layers
504
and
505
, interlayer insulating films
506
a
and
506
b
of a double layer structure are formed. Conductive layers
504
and
505
provide a word line WL and a bit line BL, respectively.
The memory cell further includes a conductive layer
510
connected electrically to impurity region
502
b
via a contact hole formed in interlayer insulating films
506
a
and
506
b,
and a conductive layer
514
arranged facing to the top of conductive layer
510
. Conductive layer
510
is formed having a V-shaped cross section, and conductive layer
514
includes a protrusion
514
a
extending into the V-shaped region at the upper region of conductive layer
510
with a capacitor insulating film
512
interposed therebetween. Conductive layer
510
functions as a connection node between an access transistor and a memory cell capacitor of the memory cell, i.e., a storage node SN. The memory cell capacitor Cs is formed in the region where conductive layers
510
and
514
face each other via capacitor insulating film
512
.
It is assumed that, in the memory cell shown in
FIG. 16
, word line WL is maintained at a ground voltage GND level, a bit line voltage Vbl is applied to bit line BL, and a voltage Vch corresponding to H level data is held on storage node SN. A cell plate voltage Vcp (a voltage between the voltages corresponding to H level data and L level data) is applied to conductive layer
514
serving as a cell plate electrode layer CP.
Main leakage sources in the memory cell are: (1) a substrate leakage current Ils flowing to P type substrate
500
via the PN junction between impurity region
502
b
and P type substrate
500
in memory cell capacitor Cs, and (2) a leakage current Ilb flowing toward bit line BL that is determined by subthreshold characteristics of the access transistor.
The magnitude of leakage current Ils to P type substrate
500
depends on a potential difference Vpn applied across the PN junction between impurity region
502
b
and P type substrate
500
. A greater potential differential Vpn increases leakage current Ils. In
FIG. 16
, the voltage on storage node SN is voltage Vch corresponding to H level data and a bias voltage Vbb is applied to P type substrate
500
. Accordingly, the potential difference Vpn is represented by the following expression.
Vpn=Vch−Vbb
Leakage current Ilb flowing toward bit line BL via the access transistor is represented by the following expression using a difference between a gate-source voltage Vgs of the access transistor and a threshold voltage Vth.
Ilb=Ilb
0·10{circumflex over ( )}[(
Vgs−Vth
)/
S]
  (1)
Here, “” represents power. In expression (1), Ilb
0
represents a current value defining threshold voltage Vth, and S is a coefficient determined by the transistor structure and the process and is represented by dVgs/dlogId. Here, Id represents a drain current. Expression (1) indicates that the bit line leakage current Ilb is strongly dependent on a gate-source voltage of an access transistor MT. The value of the leakage current Ilb becomes worst when the bit line is at L level. In a conventional case, the L level is equal to ground voltage GND level.
It seems from expression (1) that leakage current Ilb is independent of voltage Vbl of bit line BL connected to the access transistor. However, threshold voltage Vth depends on a substrate-source voltage Vbs=Vbb−Vbl. If bias voltage Vbb is a non-positive voltage and the bit line voltage or source voltage Vbl is lower, the absolute value of substrate-source voltage Vbs is smaller and threshold voltage Vth is also smaller.
For example, in a memory block to be refreshed, if a memory cell among the memory cells connected to a non-selected word line has an associated bit line swung to a voltage corresponding to L level data, an access transistor of the memory cell connected to the non-selected word line has substrate-source voltage Vbs smaller in absolute value, and bit line leakage cu

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