Internal traffic in a telecommunications node

Details Internal traffic in a telecommunications node Internal traffic in a telecommunications node

2000-09-27

2002-08-06

Vu, Huy D. (Department: 2663)

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

C370S409000

Reexamination Certificate

active

06430189

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to arranging traffic within telecommunication equipment and internal traffic between a plurality of telecommunication equipment. In particular, the invention relates to internal traffic in a node of a broadband telecommunication network, such as an ATM node.
BACKGROUND OF THE INVENTION
The architecture of a modern digital exchange is illustrated in FIG.
1
. The basic function of the exchange is to connect the exchange input port to the correct output port, in other words, to connect an incoming call on a specific incoming circuit to an outgoing call on a specific outgoing circuit. In practice, the information in a specific input side PCM timeslot is connected to a specific PCM timeslot at the output side. The incoming circuits, whether backbone lines or subscriber lines, are connected to the exchange by line interfaces. A switching matrix interconnects incoming and outgoing speech channel timeslots, and also the signalling channels and internal data channels of the exchange are connected through it.
The core of the system is the exchange control whose functions have been distributed over a plurality of units, denoted in the figure with general reference marks Unit
1
, . . . , Unit N, each carrying out its own task. As examples of such units are mentioned a unit controlling the switching matrix, signalling units carrying out different types of signalling and supervision at the input and output sides, a unit collecting call-specific charging data, a unit gathering statistics, etc. Each unit comprises at least one central processing unit CPU, a bus adapter and memory. Thus, each unit actually constitutes a computer.
The units must be able to negotiate with each other, so this exchange-internal traffic has to be arranged in some way. The most common way is to set up a dedicated common message bus, as done in,
FIG. 1
, into which the units are connected via the bus adapter. Also, the data transmitted by the exchange units to units of another exchange can be considered to be internal traffic. A typical example of this are the various types of messages exchanged in connection with the call set-up phase. Therefore, depending on the case, the common resources shared by internal traffic are the message bus, switching stage and the trunk circuits between nodes.
The exchange additionally comprises an Operation and Maintenance Unit (OAM), taking care of the maintenance of the system.
This prior art architecture is based on the use of a common message bus which carries traffic between the units. The main part of that traffic thus passes isolated from the other traffic passing through the exchange. The exchange switching matrix connects the signalling messages sent by the nodes to other nodes, to the appropriate circuit and correspondingly the switching stage forwards the messages received from the circuits for this node to the correct units.
Apart from the type described above, the telecommunication network nodes may also be ATM nodes (Asynchronous Transfer Mode), as is nowadays the case more and more often. ATM is a connection-oriented, packet switched, general purpose and scalable data transmission method in which information is sent in fixed-length cells. The cell consists of a five-byte-long header and a 48-byte-long information section. The header fields include a Virtual Path Indicator (VPI) and a Virtual Channel Indicator (VCI). At the ATM switch, the cells are transferred from a logical input channel to one or more logical output channels. The logical channel consists of the number of the physical link (e.g. optical cable) and the channel identifier on this link, in other words the VPI/VCI information. One physical transfer medium, such as an optical cable, may comprise a plurality of virtual paths VP and each virtual path comprises a plurality of virtual channels VC.
Because the cells are of a fixed length, the connections at ATM switches can be performed at equipment level on the basis of the cell header, and therefore at very high speed. Cells belonging to different connections are distinguished from each other on the basis of the virtual path (VPI) and the virtual channel (VCI) identifier. As the connection is set up, a fixed route is determined through the network, i.e. a virtual link along which the cells of the connection are routed. Based on the VPINCI values, the cells are switched at the network nodes. The VPINCI values are transmission link specific and consequently usually change in connection with switching at VP or VC level. At the end of the data transfer, the connection is released.
FIG. 2
illustrates a simplified ATM switch. It consists of input stages and output stages, into which the physical input and output fibres are connected, and of a switching stage. The input and output stages constitute the external network interfaces. The interface type may be either UNI (User Network Interface) or NNI (Network Network Interface). The input stage reads the address information, i.e. VPI and VCI identifiers, of the cell received from the input link and converts them into new VPINCI values which the output stage inserts into the header of the cell sent to the output link. The conversion is carried out with the aid of a conversion table, and at the same time the switching stage is informed of which output link the switching stage is to direct the cell in question.
The software of the switch is distributed over functional blocks, processor units
1
, . . . n, handled by computers. The most complex tasks may be left for the central processor to handle. The computers are nearly always of the embedded type, meaning that display units and other peripheral devices are not required.
As the figure indicates, the architecture of the ATM switch greatly resembles that of an STM switch; after all, the basic task of them both is the same, e.g. to connect information from an input link to an output link.
FIG. 3
is a more detailed illustration of an ATM switch. A cell, either of UNI or NNI type, from optical fibre
7
is received at circuit
31
of the PHY layer that terminates the line. The PHY (Physical Layer) carries out transmission system specific tasks at the bit level and is responsible for cell adaptation to each of the transmission systems, as well as for cell masking, cell header error checks, and cell rate justification.
From circuit
31
of the PHY layer, the cell passes to circuit
32
of the ATM layer over the interface. The ATM layer only deals with the cell header, its task being cell switching, multiplexing and demultiplexing, cell header generation and removal, as well as flow control at the User Network Interface (UNI). Additional tasks for the ATM layer include header error detection and correction, as well as block synchronization. Above the ATM layer, the AAL (ATM Adaptation Layer) fragments the higher layer frames and reassembles them at the other end, in other words, carries out the SAR (Segmentation and Reassembly) function.
The above interface has been standardized by the ATM Forum as UTOPIA, and it has become the de facto industrial standard followed by all the manufacturers of integrated ATM circuits. Over the interface, nothing but ATM cell data is transmitted, which includes control signals required by the two-way transfer, i.e. the so-called handshaking signals.
Circuit
32
of the ATM layer sends the cell to the input buffer of ATM switching stage
33
. From there, the stage connects it to the other side of the stage, to output port
35
. At the output port, the VPI/VCI value in the cell address field is examined, and the cell is transmitted to the correct virtual channel.
The processor units in FIG.
2
and the processor units in other nodes must be able to negotiate with each other. One way to arrange node-internal traffic is to connect the processor units to a common bus, which is done in the case of the switch in FIG.
1
.
Another way is to send the internal-traffic cells among other traffic, as illustrated in FIG.
4
. Here, the applications of processor units Unit
1
, . . . , unit N may directl

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